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glaserf
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[csrng/rtl] Remove the updreq FIFO from ctr_drbg_upd
The input data is now taken directly from either the output FIFO in ctr_drbg_gen or the state db and the adata unpacker, depending on the origin of the request. Signed-off-by: Florian Glaser <[email protected]>
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13 files changed

+36
-158
lines changed

13 files changed

+36
-158
lines changed

‎hw/ip/csrng/data/csrng.hjson‎

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -746,15 +746,6 @@
746746
This bit will stay set until the next reset.
747747
'''
748748
}
749-
{ bits: "5",
750-
name: "SFIFO_UPDREQ_ERR",
751-
desc: '''
752-
This bit will be set to one when an error has been detected for the
753-
updreq FIFO. The type of error is reflected in the type status
754-
bits (bits 28 through 30 of this register).
755-
This bit will stay set until the next reset.
756-
'''
757-
}
758749
{ bits: "7",
759750
name: "SFIFO_BENCACK_ERR",
760751
desc: '''

‎hw/ip/csrng/doc/registers.md‎

Lines changed: 3 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -555,12 +555,12 @@ Writing a zero resets this status bit.
555555
Hardware detection of error conditions status register
556556
- Offset: `0x54`
557557
- Reset default: `0x0`
558-
- Reset mask: `0x77f0febb`
558+
- Reset mask: `0x77f0fe9b`
559559

560560
### Fields
561561

562562
```wavejson
563-
{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_RCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_UPDREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_BENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
563+
{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_RCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "SFIFO_BENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
564564
```
565565

566566
| Bits | Type | Reset | Name |
@@ -587,8 +587,7 @@ Hardware detection of error conditions status register
587587
| 9 | ro | 0x0 | [SFIFO_FINAL_ERR](#err_code--sfifo_final_err) |
588588
| 8 | | | Reserved |
589589
| 7 | ro | 0x0 | [SFIFO_BENCACK_ERR](#err_code--sfifo_bencack_err) |
590-
| 6 | | | Reserved |
591-
| 5 | ro | 0x0 | [SFIFO_UPDREQ_ERR](#err_code--sfifo_updreq_err) |
590+
| 6:5 | | | Reserved |
592591
| 4 | ro | 0x0 | [SFIFO_KEYVRC_ERR](#err_code--sfifo_keyvrc_err) |
593592
| 3 | ro | 0x0 | [SFIFO_RCSTAGE_ERR](#err_code--sfifo_rcstage_err) |
594593
| 2 | | | Reserved |
@@ -704,12 +703,6 @@ bencack FIFO. The type of error is reflected in the type status
704703
bits (bits 28 through 30 of this register).
705704
This bit will stay set until the next reset.
706705

707-
### ERR_CODE . SFIFO_UPDREQ_ERR
708-
This bit will be set to one when an error has been detected for the
709-
updreq FIFO. The type of error is reflected in the type status
710-
bits (bits 28 through 30 of this register).
711-
This bit will stay set until the next reset.
712-
713706
### ERR_CODE . SFIFO_KEYVRC_ERR
714707
This bit will be set to one when an error has been detected for the
715708
keyvrc FIFO. The type of error is reflected in the type status

‎hw/ip/csrng/dv/env/csrng_env_pkg.sv‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,6 @@ package csrng_env_pkg;
5858
sfifo_genbits_error = 1,
5959
sfifo_rcstage_error = 3,
6060
sfifo_keyvrc_error = 4,
61-
sfifo_updreq_error = 5,
6261
sfifo_bencack_error = 7,
6362
sfifo_final_error = 9,
6463
sfifo_gbencack_error = 10,
@@ -85,7 +84,6 @@ package csrng_env_pkg;
8584
sfifo_genbits_err = 1,
8685
sfifo_rcstage_err = 3,
8786
sfifo_keyvrc_err = 4,
88-
sfifo_updreq_err = 5,
8987
sfifo_bencack_err = 7,
9088
sfifo_final_err = 9,
9189
sfifo_gbencack_err = 10,
@@ -109,7 +107,6 @@ package csrng_env_pkg;
109107
sfifo_genbits_err_test = 27,
110108
sfifo_rcstage_err_test = 29,
111109
sfifo_keyvrc_err_test = 30,
112-
sfifo_updreq_err_test = 31,
113110
sfifo_bencack_err_test = 33,
114111
sfifo_final_err_test = 35,
115112
sfifo_gbencack_err_test = 36,
@@ -135,7 +132,6 @@ package csrng_env_pkg;
135132
SFIFO_GENBITS_ERR = 1,
136133
SFIFO_RCSTAGE_ERR = 3,
137134
SFIFO_KEYVRC_ERR = 4,
138-
SFIFO_UPDREQ_ERR = 5,
139135
SFIFO_BENCACK_ERR = 7,
140136
SFIFO_FINAL_ERR = 9,
141137
SFIFO_GBENCACK_ERR = 10,
@@ -176,7 +172,6 @@ package csrng_env_pkg;
176172
sfifo_gbencack = 5,
177173
sfifo_final = 6,
178174
sfifo_bencack = 8,
179-
sfifo_updreq = 10,
180175
sfifo_keyvrc = 11,
181176
sfifo_rcstage = 12,
182177
sfifo_genbits = 14,

‎hw/ip/csrng/dv/env/csrng_path_if.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ interface csrng_path_if
1919
".u_csrng_cmd_stage.", fifo_name, "_", which_path};
2020
"sfifo_rcstage", "sfifo_keyvrc": return {core_path, ".u_csrng_ctr_drbg_cmd.",
2121
fifo_name, "_", which_path};
22-
"sfifo_updreq", "sfifo_bencack", "sfifo_final": return
22+
"sfifo_bencack", "sfifo_final": return
2323
{core_path, ".u_csrng_ctr_drbg_upd.", fifo_name, "_", which_path};
2424
"sfifo_gbencack", "sfifo_grcstage", "sfifo_ggenreq", "sfifo_gadstage", "sfifo_ggenbits":
2525
return {core_path,".u_csrng_ctr_drbg_gen.sfifo_", fifo_name.substr(7, fifo_name.len()-1),

‎hw/ip/csrng/dv/env/seq_lib/csrng_err_vseq.sv‎

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,7 @@ class csrng_err_vseq extends csrng_base_vseq;
101101
case (cfg.which_err_code) inside
102102
sfifo_cmd_err, sfifo_genbits_err, sfifo_rcstage_err, sfifo_keyvrc_err,
103103
sfifo_final_err, sfifo_gbencack_err, sfifo_grcstage_err,
104-
sfifo_gadstage_err, sfifo_ggenbits_err, sfifo_cmdid_err, sfifo_updreq_err,
104+
sfifo_gadstage_err, sfifo_ggenbits_err, sfifo_cmdid_err,
105105
sfifo_bencack_err, sfifo_ggenreq_err: begin
106106
fld = csr.get_field_by_name(fld_name);
107107
fifo_base_path = fld_name.substr(0, last_index-1);
@@ -114,8 +114,8 @@ class csrng_err_vseq extends csrng_base_vseq;
114114
`uvm_info(`gfn, $sformatf("Forcing this FIFO error type %s", cfg.which_fifo_err.name()),
115115
UVM_MEDIUM)
116116

117-
if (cfg.which_err_code == sfifo_updreq_err || cfg.which_err_code == sfifo_bencack_err ||
118-
cfg.which_err_code == sfifo_ggenreq_err) begin
117+
if (cfg.which_err_code == sfifo_ggenreq_err ||
118+
cfg.which_err_code == sfifo_bencack_err) begin
119119
force_all_fifo_errs_exception(fifo_forced_paths, fifo_forced_values, path_exts, fld,
120120
1'b1, cfg.which_fifo_err);
121121

@@ -263,9 +263,7 @@ class csrng_err_vseq extends csrng_base_vseq;
263263
value2 = fifo_err_value[1][path_key];
264264

265265
if (cfg.which_err_code == fifo_read_error &&
266-
((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_bencack) ||
267-
(cfg.which_fifo == sfifo_updreq)))
268-
begin
266+
((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_bencack))) begin
269267
force_fifo_err_exception(path1, path2, 1'b1, 1'b0, 1'b0, fld, 1'b1);
270268

271269
// For sfifo_gadstage the down stream FIFO also takes inputs from sources other than
@@ -304,7 +302,7 @@ class csrng_err_vseq extends csrng_base_vseq;
304302
cov_vif.cg_err_code_sample(.err_code(backdoor_err_code_val));
305303
end
306304
sfifo_cmd_err_test, sfifo_genbits_err_test, sfifo_rcstage_err_test,
307-
sfifo_keyvrc_err_test, sfifo_updreq_err_test, sfifo_bencack_err_test,
305+
sfifo_keyvrc_err_test, sfifo_bencack_err_test,
308306
sfifo_final_err_test, sfifo_gbencack_err_test, sfifo_grcstage_err_test,
309307
sfifo_ggenreq_err_test, sfifo_gadstage_err_test, sfifo_ggenbits_err_test,
310308
sfifo_cmdid_err_test, cmd_stage_sm_err_test, main_sm_err_test, drbg_gen_sm_err_test,

‎hw/ip/csrng/dv/env/seq_lib/csrng_intr_vseq.sv‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -223,15 +223,14 @@ class csrng_intr_vseq extends csrng_base_vseq;
223223
sfifo_cmd_error, sfifo_genbits_error, sfifo_rcstage_error,
224224
sfifo_keyvrc_error, sfifo_final_error, sfifo_gbencack_error,
225225
sfifo_grcstage_error, sfifo_gadstage_error, sfifo_ggenbits_error,
226-
sfifo_cmdid_error, sfifo_updreq_error, sfifo_bencack_error, sfifo_ggenreq_error: begin
226+
sfifo_cmdid_error, sfifo_bencack_error, sfifo_ggenreq_error: begin
227227
fifo_base_path = fld_name.substr(0, last_index-1);
228228

229229
foreach (path_exts[i]) begin
230230
fifo_forced_paths[i] = cfg.csrng_path_vif.fifo_err_path(cfg.NHwApps, fifo_base_path,
231231
path_exts[i]);
232232
end
233-
if (cfg.which_fatal_err == sfifo_updreq_error ||
234-
cfg.which_fatal_err == sfifo_bencack_error ||
233+
if (cfg.which_fatal_err == sfifo_bencack_error ||
235234
cfg.which_fatal_err == sfifo_ggenreq_error) begin
236235
force_all_fifo_errs_exception(fifo_forced_paths, fifo_forced_values, path_exts,
237236
ral.intr_state.cs_fatal_err, 1'b1, cfg.which_fifo_err);
@@ -310,9 +309,7 @@ class csrng_intr_vseq extends csrng_base_vseq;
310309
value2 = fifo_err_value[1][path_key];
311310

312311
if (cfg.which_fatal_err == fifo_read_error &&
313-
((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_bencack) ||
314-
(cfg.which_fifo == sfifo_updreq)))
315-
begin
312+
((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_bencack))) begin
316313
force_fifo_err_exception(path1, path2, value1, value2, 1'b0, ral.intr_state.cs_fatal_err,
317314
1'b1);
318315
end else begin

‎hw/ip/csrng/rtl/csrng_core.sv‎

Lines changed: 2 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -139,8 +139,6 @@ module csrng_core import csrng_pkg::*; #(
139139
logic [2:0] ctr_drbg_cmd_sfifo_rcstage_err;
140140
logic ctr_drbg_cmd_sfifo_keyvrc_err_sum;
141141
logic [2:0] ctr_drbg_cmd_sfifo_keyvrc_err;
142-
logic ctr_drbg_upd_sfifo_updreq_err_sum;
143-
logic [2:0] ctr_drbg_upd_sfifo_updreq_err;
144142
logic ctr_drbg_upd_sfifo_bencack_err_sum;
145143
logic [2:0] ctr_drbg_upd_sfifo_bencack_err;
146144
logic ctr_drbg_upd_sfifo_final_err_sum;
@@ -432,7 +430,6 @@ module csrng_core import csrng_pkg::*; #(
432430
(|cmd_stage_sfifo_genbits_err_sum) ||
433431
ctr_drbg_cmd_sfifo_rcstage_err_sum ||
434432
ctr_drbg_cmd_sfifo_keyvrc_err_sum ||
435-
ctr_drbg_upd_sfifo_updreq_err_sum ||
436433
ctr_drbg_upd_sfifo_bencack_err_sum ||
437434
ctr_drbg_upd_sfifo_final_err_sum ||
438435
ctr_drbg_gen_sfifo_gbencack_err_sum ||
@@ -453,8 +450,6 @@ module csrng_core import csrng_pkg::*; #(
453450
err_code_test_bit[3];
454451
assign ctr_drbg_cmd_sfifo_keyvrc_err_sum = (|ctr_drbg_cmd_sfifo_keyvrc_err) ||
455452
err_code_test_bit[4];
456-
assign ctr_drbg_upd_sfifo_updreq_err_sum = (|ctr_drbg_upd_sfifo_updreq_err) ||
457-
err_code_test_bit[5];
458453
assign ctr_drbg_upd_sfifo_bencack_err_sum = (|ctr_drbg_upd_sfifo_bencack_err) ||
459454
err_code_test_bit[7];
460455
assign ctr_drbg_upd_sfifo_final_err_sum = (|ctr_drbg_upd_sfifo_final_err) ||
@@ -494,7 +489,6 @@ module csrng_core import csrng_pkg::*; #(
494489
ctr_drbg_gen_sfifo_gbencack_err[2] ||
495490
ctr_drbg_upd_sfifo_final_err[2] ||
496491
ctr_drbg_upd_sfifo_bencack_err[2] ||
497-
ctr_drbg_upd_sfifo_updreq_err[2] ||
498492
ctr_drbg_cmd_sfifo_keyvrc_err[2] ||
499493
ctr_drbg_cmd_sfifo_rcstage_err[2] ||
500494
(|cmd_stage_sfifo_genbits_err_wr) ||
@@ -509,7 +503,6 @@ module csrng_core import csrng_pkg::*; #(
509503
ctr_drbg_gen_sfifo_gbencack_err[1] ||
510504
ctr_drbg_upd_sfifo_final_err[1] ||
511505
ctr_drbg_upd_sfifo_bencack_err[1] ||
512-
ctr_drbg_upd_sfifo_updreq_err[1] ||
513506
ctr_drbg_cmd_sfifo_keyvrc_err[1] ||
514507
ctr_drbg_cmd_sfifo_rcstage_err[1] ||
515508
(|cmd_stage_sfifo_genbits_err_rd) ||
@@ -524,7 +517,6 @@ module csrng_core import csrng_pkg::*; #(
524517
ctr_drbg_gen_sfifo_gbencack_err[0] ||
525518
ctr_drbg_upd_sfifo_final_err[0] ||
526519
ctr_drbg_upd_sfifo_bencack_err[0] ||
527-
ctr_drbg_upd_sfifo_updreq_err[0] ||
528520
ctr_drbg_cmd_sfifo_keyvrc_err[0] ||
529521
ctr_drbg_cmd_sfifo_rcstage_err[0] ||
530522
(|cmd_stage_sfifo_genbits_err_st) ||
@@ -548,10 +540,6 @@ module csrng_core import csrng_pkg::*; #(
548540
assign hw2reg.err_code.sfifo_keyvrc_err.de = cs_enable_fo[6] &&
549541
ctr_drbg_cmd_sfifo_keyvrc_err_sum;
550542

551-
assign hw2reg.err_code.sfifo_updreq_err.d = 1'b1;
552-
assign hw2reg.err_code.sfifo_updreq_err.de = cs_enable_fo[7] &&
553-
ctr_drbg_upd_sfifo_updreq_err_sum;
554-
555543
assign hw2reg.err_code.sfifo_bencack_err.d = 1'b1;
556544
assign hw2reg.err_code.sfifo_bencack_err.de = cs_enable_fo[9] &&
557545
ctr_drbg_upd_sfifo_bencack_err_sum;
@@ -1287,7 +1275,6 @@ module csrng_core import csrng_pkg::*; #(
12871275
.block_encrypt_rsp_data_i(block_encrypt_rsp_data),
12881276

12891277
.ctr_err_o (ctr_drbg_upd_v_ctr_err),
1290-
.fifo_updreq_err_o (ctr_drbg_upd_sfifo_updreq_err),
12911278
.fifo_bencack_err_o (ctr_drbg_upd_sfifo_bencack_err),
12921279
.fifo_final_err_o (ctr_drbg_upd_sfifo_final_err),
12931280
.sm_block_enc_req_err_o(drbg_updbe_sm_err),
@@ -1500,9 +1487,9 @@ module csrng_core import csrng_pkg::*; #(
15001487
logic unused_state_db_inst_state;
15011488

15021489
assign unused_err_code_test_bit = (|err_code_test_bit[19:16]) || (|err_code_test_bit[27:26]) ||
1503-
err_code_test_bit[8] || err_code_test_bit[6] ||
1490+
err_code_test_bit[8] || (|err_code_test_bit[6:5]) ||
15041491
err_code_test_bit[2];
1505-
assign unused_enable_fo = cs_enable_fo[10] || cs_enable_fo[8] || cs_enable_fo[4];
1492+
assign unused_enable_fo = cs_enable_fo[10] || (|cs_enable_fo[8:7]) || cs_enable_fo[4];
15061493
assign unused_reg2hw_genbits = (|reg2hw.genbits.q);
15071494
assign unused_int_state_val = (|reg2hw.int_state_val.q);
15081495
assign unused_reseed_interval = reg2hw.reseed_interval.qe;

‎hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,7 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; (
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req_data = req_data_i;
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// Insert the FIPS info from entropy source on instantiate and reseed commands.
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// Else, keep the existing info (from state db).
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req_data.fips = ((req_data_i.cmd == INS) || (req_data_i.cmd == RES)) ?
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req_data.fips = ((req_data_i.cmd == INS) || (req_data_i.cmd == RES)) ?
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req_entropy_fips_i : req_data_i.fips;
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end
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