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[csrng/rtl] Remove the bencreq FIFO from ctr_drbg_upd
This commit bridges the bencreq FIFO and instead feeds the read data from the updreq FIFO to the block_encrypt. This has neither functional nor timing impacts. Signed-off-by: Florian Glaser <[email protected]>
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12 files changed

+27
-140
lines changed

12 files changed

+27
-140
lines changed

‎hw/ip/csrng/data/csrng.hjson‎

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -755,15 +755,6 @@
755755
This bit will stay set until the next reset.
756756
'''
757757
}
758-
{ bits: "6",
759-
name: "SFIFO_BENCREQ_ERR",
760-
desc: '''
761-
This bit will be set to one when an error has been detected for the
762-
bencreq FIFO. The type of error is reflected in the type status
763-
bits (bits 28 through 30 of this register).
764-
This bit will stay set until the next reset.
765-
'''
766-
}
767758
{ bits: "7",
768759
name: "SFIFO_BENCACK_ERR",
769760
desc: '''

‎hw/ip/csrng/doc/registers.md‎

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -555,12 +555,12 @@ Writing a zero resets this status bit.
555555
Hardware detection of error conditions status register
556556
- Offset: `0x54`
557557
- Reset default: `0x0`
558-
- Reset mask: `0x77f0fefb`
558+
- Reset mask: `0x77f0febb`
559559

560560
### Fields
561561

562562
```wavejson
563-
{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_RCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_UPDREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_BENCREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_BENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
563+
{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_RCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_UPDREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_BENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
564564
```
565565

566566
| Bits | Type | Reset | Name |
@@ -587,7 +587,7 @@ Hardware detection of error conditions status register
587587
| 9 | ro | 0x0 | [SFIFO_FINAL_ERR](#err_code--sfifo_final_err) |
588588
| 8 | | | Reserved |
589589
| 7 | ro | 0x0 | [SFIFO_BENCACK_ERR](#err_code--sfifo_bencack_err) |
590-
| 6 | ro | 0x0 | [SFIFO_BENCREQ_ERR](#err_code--sfifo_bencreq_err) |
590+
| 6 | | | Reserved |
591591
| 5 | ro | 0x0 | [SFIFO_UPDREQ_ERR](#err_code--sfifo_updreq_err) |
592592
| 4 | ro | 0x0 | [SFIFO_KEYVRC_ERR](#err_code--sfifo_keyvrc_err) |
593593
| 3 | ro | 0x0 | [SFIFO_RCSTAGE_ERR](#err_code--sfifo_rcstage_err) |
@@ -704,12 +704,6 @@ bencack FIFO. The type of error is reflected in the type status
704704
bits (bits 28 through 30 of this register).
705705
This bit will stay set until the next reset.
706706

707-
### ERR_CODE . SFIFO_BENCREQ_ERR
708-
This bit will be set to one when an error has been detected for the
709-
bencreq FIFO. The type of error is reflected in the type status
710-
bits (bits 28 through 30 of this register).
711-
This bit will stay set until the next reset.
712-
713707
### ERR_CODE . SFIFO_UPDREQ_ERR
714708
This bit will be set to one when an error has been detected for the
715709
updreq FIFO. The type of error is reflected in the type status

‎hw/ip/csrng/dv/env/csrng_env_pkg.sv‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,6 @@ package csrng_env_pkg;
5959
sfifo_rcstage_error = 3,
6060
sfifo_keyvrc_error = 4,
6161
sfifo_updreq_error = 5,
62-
sfifo_bencreq_error = 6,
6362
sfifo_bencack_error = 7,
6463
sfifo_final_error = 9,
6564
sfifo_gbencack_error = 10,
@@ -87,7 +86,6 @@ package csrng_env_pkg;
8786
sfifo_rcstage_err = 3,
8887
sfifo_keyvrc_err = 4,
8988
sfifo_updreq_err = 5,
90-
sfifo_bencreq_err = 6,
9189
sfifo_bencack_err = 7,
9290
sfifo_final_err = 9,
9391
sfifo_gbencack_err = 10,
@@ -112,7 +110,6 @@ package csrng_env_pkg;
112110
sfifo_rcstage_err_test = 29,
113111
sfifo_keyvrc_err_test = 30,
114112
sfifo_updreq_err_test = 31,
115-
sfifo_bencreq_err_test = 32,
116113
sfifo_bencack_err_test = 33,
117114
sfifo_final_err_test = 35,
118115
sfifo_gbencack_err_test = 36,
@@ -139,7 +136,6 @@ package csrng_env_pkg;
139136
SFIFO_RCSTAGE_ERR = 3,
140137
SFIFO_KEYVRC_ERR = 4,
141138
SFIFO_UPDREQ_ERR = 5,
142-
SFIFO_BENCREQ_ERR = 6,
143139
SFIFO_BENCACK_ERR = 7,
144140
SFIFO_FINAL_ERR = 9,
145141
SFIFO_GBENCACK_ERR = 10,
@@ -180,7 +176,6 @@ package csrng_env_pkg;
180176
sfifo_gbencack = 5,
181177
sfifo_final = 6,
182178
sfifo_bencack = 8,
183-
sfifo_bencreq = 9,
184179
sfifo_updreq = 10,
185180
sfifo_keyvrc = 11,
186181
sfifo_rcstage = 12,

‎hw/ip/csrng/dv/env/csrng_path_if.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ interface csrng_path_if
1919
".u_csrng_cmd_stage.", fifo_name, "_", which_path};
2020
"sfifo_rcstage", "sfifo_keyvrc": return {core_path, ".u_csrng_ctr_drbg_cmd.",
2121
fifo_name, "_", which_path};
22-
"sfifo_updreq", "sfifo_bencreq", "sfifo_bencack", "sfifo_final": return
22+
"sfifo_updreq", "sfifo_bencack", "sfifo_final": return
2323
{core_path, ".u_csrng_ctr_drbg_upd.", fifo_name, "_", which_path};
2424
"sfifo_gbencack", "sfifo_grcstage", "sfifo_ggenreq", "sfifo_gadstage", "sfifo_ggenbits":
2525
return {core_path,".u_csrng_ctr_drbg_gen.sfifo_", fifo_name.substr(7, fifo_name.len()-1),

‎hw/ip/csrng/dv/env/seq_lib/csrng_err_vseq.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ class csrng_err_vseq extends csrng_base_vseq;
100100

101101
case (cfg.which_err_code) inside
102102
sfifo_cmd_err, sfifo_genbits_err, sfifo_rcstage_err, sfifo_keyvrc_err,
103-
sfifo_bencreq_err, sfifo_final_err, sfifo_gbencack_err, sfifo_grcstage_err,
103+
sfifo_final_err, sfifo_gbencack_err, sfifo_grcstage_err,
104104
sfifo_gadstage_err, sfifo_ggenbits_err, sfifo_cmdid_err, sfifo_updreq_err,
105105
sfifo_bencack_err, sfifo_ggenreq_err: begin
106106
fld = csr.get_field_by_name(fld_name);
@@ -304,7 +304,7 @@ class csrng_err_vseq extends csrng_base_vseq;
304304
cov_vif.cg_err_code_sample(.err_code(backdoor_err_code_val));
305305
end
306306
sfifo_cmd_err_test, sfifo_genbits_err_test, sfifo_rcstage_err_test,
307-
sfifo_keyvrc_err_test, sfifo_updreq_err_test, sfifo_bencreq_err_test, sfifo_bencack_err_test,
307+
sfifo_keyvrc_err_test, sfifo_updreq_err_test, sfifo_bencack_err_test,
308308
sfifo_final_err_test, sfifo_gbencack_err_test, sfifo_grcstage_err_test,
309309
sfifo_ggenreq_err_test, sfifo_gadstage_err_test, sfifo_ggenbits_err_test,
310310
sfifo_cmdid_err_test, cmd_stage_sm_err_test, main_sm_err_test, drbg_gen_sm_err_test,

‎hw/ip/csrng/dv/env/seq_lib/csrng_intr_vseq.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -221,7 +221,7 @@ class csrng_intr_vseq extends csrng_base_vseq;
221221

222222
case (cfg.which_fatal_err) inside
223223
sfifo_cmd_error, sfifo_genbits_error, sfifo_rcstage_error,
224-
sfifo_keyvrc_error, sfifo_bencreq_error, sfifo_final_error, sfifo_gbencack_error,
224+
sfifo_keyvrc_error, sfifo_final_error, sfifo_gbencack_error,
225225
sfifo_grcstage_error, sfifo_gadstage_error, sfifo_ggenbits_error,
226226
sfifo_cmdid_error, sfifo_updreq_error, sfifo_bencack_error, sfifo_ggenreq_error: begin
227227
fifo_base_path = fld_name.substr(0, last_index-1);

‎hw/ip/csrng/rtl/csrng_core.sv‎

Lines changed: 3 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -141,8 +141,6 @@ module csrng_core import csrng_pkg::*; #(
141141
logic [2:0] ctr_drbg_cmd_sfifo_keyvrc_err;
142142
logic ctr_drbg_upd_sfifo_updreq_err_sum;
143143
logic [2:0] ctr_drbg_upd_sfifo_updreq_err;
144-
logic ctr_drbg_upd_sfifo_bencreq_err_sum;
145-
logic [2:0] ctr_drbg_upd_sfifo_bencreq_err;
146144
logic ctr_drbg_upd_sfifo_bencack_err_sum;
147145
logic [2:0] ctr_drbg_upd_sfifo_bencack_err;
148146
logic ctr_drbg_upd_sfifo_final_err_sum;
@@ -435,7 +433,6 @@ module csrng_core import csrng_pkg::*; #(
435433
ctr_drbg_cmd_sfifo_rcstage_err_sum ||
436434
ctr_drbg_cmd_sfifo_keyvrc_err_sum ||
437435
ctr_drbg_upd_sfifo_updreq_err_sum ||
438-
ctr_drbg_upd_sfifo_bencreq_err_sum ||
439436
ctr_drbg_upd_sfifo_bencack_err_sum ||
440437
ctr_drbg_upd_sfifo_final_err_sum ||
441438
ctr_drbg_gen_sfifo_gbencack_err_sum ||
@@ -458,8 +455,6 @@ module csrng_core import csrng_pkg::*; #(
458455
err_code_test_bit[4];
459456
assign ctr_drbg_upd_sfifo_updreq_err_sum = (|ctr_drbg_upd_sfifo_updreq_err) ||
460457
err_code_test_bit[5];
461-
assign ctr_drbg_upd_sfifo_bencreq_err_sum = (|ctr_drbg_upd_sfifo_bencreq_err) ||
462-
err_code_test_bit[6];
463458
assign ctr_drbg_upd_sfifo_bencack_err_sum = (|ctr_drbg_upd_sfifo_bencack_err) ||
464459
err_code_test_bit[7];
465460
assign ctr_drbg_upd_sfifo_final_err_sum = (|ctr_drbg_upd_sfifo_final_err) ||
@@ -499,7 +494,6 @@ module csrng_core import csrng_pkg::*; #(
499494
ctr_drbg_gen_sfifo_gbencack_err[2] ||
500495
ctr_drbg_upd_sfifo_final_err[2] ||
501496
ctr_drbg_upd_sfifo_bencack_err[2] ||
502-
ctr_drbg_upd_sfifo_bencreq_err[2] ||
503497
ctr_drbg_upd_sfifo_updreq_err[2] ||
504498
ctr_drbg_cmd_sfifo_keyvrc_err[2] ||
505499
ctr_drbg_cmd_sfifo_rcstage_err[2] ||
@@ -515,7 +509,6 @@ module csrng_core import csrng_pkg::*; #(
515509
ctr_drbg_gen_sfifo_gbencack_err[1] ||
516510
ctr_drbg_upd_sfifo_final_err[1] ||
517511
ctr_drbg_upd_sfifo_bencack_err[1] ||
518-
ctr_drbg_upd_sfifo_bencreq_err[1] ||
519512
ctr_drbg_upd_sfifo_updreq_err[1] ||
520513
ctr_drbg_cmd_sfifo_keyvrc_err[1] ||
521514
ctr_drbg_cmd_sfifo_rcstage_err[1] ||
@@ -531,7 +524,6 @@ module csrng_core import csrng_pkg::*; #(
531524
ctr_drbg_gen_sfifo_gbencack_err[0] ||
532525
ctr_drbg_upd_sfifo_final_err[0] ||
533526
ctr_drbg_upd_sfifo_bencack_err[0] ||
534-
ctr_drbg_upd_sfifo_bencreq_err[0] ||
535527
ctr_drbg_upd_sfifo_updreq_err[0] ||
536528
ctr_drbg_cmd_sfifo_keyvrc_err[0] ||
537529
ctr_drbg_cmd_sfifo_rcstage_err[0] ||
@@ -560,10 +552,6 @@ module csrng_core import csrng_pkg::*; #(
560552
assign hw2reg.err_code.sfifo_updreq_err.de = cs_enable_fo[7] &&
561553
ctr_drbg_upd_sfifo_updreq_err_sum;
562554

563-
assign hw2reg.err_code.sfifo_bencreq_err.d = 1'b1;
564-
assign hw2reg.err_code.sfifo_bencreq_err.de = cs_enable_fo[8] &&
565-
ctr_drbg_upd_sfifo_bencreq_err_sum;
566-
567555
assign hw2reg.err_code.sfifo_bencack_err.d = 1'b1;
568556
assign hw2reg.err_code.sfifo_bencack_err.de = cs_enable_fo[9] &&
569557
ctr_drbg_upd_sfifo_bencack_err_sum;
@@ -1300,7 +1288,6 @@ module csrng_core import csrng_pkg::*; #(
13001288

13011289
.ctr_err_o (ctr_drbg_upd_v_ctr_err),
13021290
.fifo_updreq_err_o (ctr_drbg_upd_sfifo_updreq_err),
1303-
.fifo_bencreq_err_o (ctr_drbg_upd_sfifo_bencreq_err),
13041291
.fifo_bencack_err_o (ctr_drbg_upd_sfifo_bencack_err),
13051292
.fifo_final_err_o (ctr_drbg_upd_sfifo_final_err),
13061293
.sm_block_enc_req_err_o(drbg_updbe_sm_err),
@@ -1513,8 +1500,9 @@ module csrng_core import csrng_pkg::*; #(
15131500
logic unused_state_db_inst_state;
15141501

15151502
assign unused_err_code_test_bit = (|err_code_test_bit[19:16]) || (|err_code_test_bit[27:26]) ||
1516-
err_code_test_bit[8] || err_code_test_bit[2];
1517-
assign unused_enable_fo = cs_enable_fo[10] | cs_enable_fo[4];
1503+
err_code_test_bit[8] || err_code_test_bit[6] ||
1504+
err_code_test_bit[2];
1505+
assign unused_enable_fo = cs_enable_fo[10] || cs_enable_fo[8] || cs_enable_fo[4];
15181506
assign unused_reg2hw_genbits = (|reg2hw.genbits.q);
15191507
assign unused_int_state_val = (|reg2hw.int_state_val.q);
15201508
assign unused_reseed_interval = reg2hw.reseed_interval.qe;

‎hw/ip/csrng/rtl/csrng_ctr_drbg_upd.sv‎

Lines changed: 8 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,6 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; (
4242
// Error status outputs
4343
output logic ctr_err_o,
4444
output logic [2:0] fifo_updreq_err_o,
45-
output logic [2:0] fifo_bencreq_err_o,
4645
output logic [2:0] fifo_bencack_err_o,
4746
output logic [2:0] fifo_final_err_o,
4847
output logic sm_block_enc_req_err_o,
@@ -60,14 +59,6 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; (
6059

6160
csrng_upd_data_t req_data_fifo;
6261

63-
// blk_encrypt_req fifo
64-
logic sfifo_bencreq_wvld;
65-
logic sfifo_bencreq_wrdy;
66-
logic [BencDataWidth-1:0] sfifo_bencreq_rdata;
67-
logic sfifo_bencreq_rvld;
68-
logic sfifo_bencreq_rrdy;
69-
logic [BencDataWidth-1:0] sfifo_bencreq_wdata;
70-
7162
// blk_encrypt_ack fifo
7263
logic sfifo_bencack_wvld;
7364
logic sfifo_bencack_wrdy;
@@ -295,7 +286,7 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; (
295286
blk_enc_state_d = blk_enc_state_q;
296287
v_ctr_load = 1'b0;
297288
v_ctr_inc = 1'b0;
298-
sfifo_bencreq_wvld = 1'b0;
289+
block_encrypt_req_vld_o = 1'b0;
299290
sm_block_enc_req_err_o = 1'b0;
300291
es_halt_ack_o = 1'b0;
301292
unique case (blk_enc_state_q)
@@ -307,7 +298,7 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; (
307298
blk_enc_state_d = ESHalt;
308299
end else if (!enable_i) begin
309300
blk_enc_state_d = ReqIdle;
310-
end else if (sfifo_updreq_rvld && sfifo_bencreq_wrdy) begin
301+
end else if (sfifo_updreq_rvld) begin
311302
v_ctr_load = 1'b1;
312303
blk_enc_state_d = ReqSend;
313304
end
@@ -316,9 +307,9 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; (
316307
if (!enable_i) begin
317308
blk_enc_state_d = ReqIdle;
318309
end else if (!block_ctr_done) begin
319-
if (sfifo_bencreq_wrdy) begin
310+
block_encrypt_req_vld_o = 1'b1;
311+
if (block_encrypt_req_rdy_i) begin
320312
v_ctr_inc = 1'b1;
321-
sfifo_bencreq_wvld = 1'b1;
322313
end
323314
end else begin
324315
// Wait for completion on the benc_rsp path
@@ -353,46 +344,11 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; (
353344
endcase
354345
end
355346

356-
//--------------------------------------------
357-
// block_encrypt request fifo for staging aes requests
358-
//--------------------------------------------
359-
360-
prim_fifo_sync #(
361-
.Width(BencDataWidth),
362-
.Pass(0),
363-
.Depth(1),
364-
.OutputZeroIfEmpty(1'b0)
365-
) u_prim_fifo_sync_bencreq (
366-
.clk_i (clk_i),
367-
.rst_ni (rst_ni),
368-
.clr_i (!enable_i),
369-
.wvalid_i(sfifo_bencreq_wvld),
370-
.wready_o(sfifo_bencreq_wrdy),
371-
.wdata_i (sfifo_bencreq_wdata),
372-
.rvalid_o(sfifo_bencreq_rvld),
373-
.rready_i(sfifo_bencreq_rrdy),
374-
.rdata_o (sfifo_bencreq_rdata),
375-
.full_o (),
376-
.depth_o (),
377-
.err_o ()
378-
);
379-
380-
assign sfifo_bencreq_rrdy = sfifo_bencreq_rvld && block_encrypt_req_rdy_i;
381-
assign block_encrypt_req_vld_o = sfifo_bencreq_rvld;
382-
383347
// Forward the upstream data together with the current counter value to block_encrypt
384-
assign sfifo_bencreq_wdata = {req_data_fifo.inst_id,
385-
req_data_fifo.cmd,
386-
req_data_fifo.key,
387-
v_ctr_sized};
388-
389-
// rdata of the FIFO is already in the correct format
390-
assign block_encrypt_req_data_o = sfifo_bencreq_rdata;
391-
392-
assign fifo_bencreq_err_o =
393-
{( sfifo_bencreq_wvld && !sfifo_bencreq_wrdy),
394-
( sfifo_bencreq_rrdy && !sfifo_bencreq_rvld),
395-
(!sfifo_bencreq_wrdy && !sfifo_bencreq_rvld)};
348+
assign block_encrypt_req_data_o = {req_data_fifo.inst_id,
349+
req_data_fifo.cmd,
350+
req_data_fifo.key,
351+
v_ctr_sized};
396352

397353
//--------------------------------------------
398354
// block_encrypt response fifo from block encrypt

‎hw/ip/csrng/rtl/csrng_reg_pkg.sv‎

Lines changed: 9 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -311,10 +311,6 @@ package csrng_reg_pkg;
311311
logic d;
312312
logic de;
313313
} sfifo_bencack_err;
314-
struct packed {
315-
logic d;
316-
logic de;
317-
} sfifo_bencreq_err;
318314
struct packed {
319315
logic d;
320316
logic de;
@@ -361,15 +357,15 @@ package csrng_reg_pkg;
361357

362358
// HW -> register type
363359
typedef struct packed {
364-
csrng_hw2reg_intr_state_reg_t intr_state; // [267:260]
365-
csrng_hw2reg_reseed_counter_mreg_t [2:0] reseed_counter; // [259:164]
366-
csrng_hw2reg_sw_cmd_sts_reg_t sw_cmd_sts; // [163:156]
367-
csrng_hw2reg_genbits_vld_reg_t genbits_vld; // [155:154]
368-
csrng_hw2reg_genbits_reg_t genbits; // [153:122]
369-
csrng_hw2reg_int_state_val_reg_t int_state_val; // [121:90]
370-
csrng_hw2reg_hw_exc_sts_reg_t hw_exc_sts; // [89:73]
371-
csrng_hw2reg_recov_alert_sts_reg_t recov_alert_sts; // [72:55]
372-
csrng_hw2reg_err_code_reg_t err_code; // [54:7]
360+
csrng_hw2reg_intr_state_reg_t intr_state; // [265:258]
361+
csrng_hw2reg_reseed_counter_mreg_t [2:0] reseed_counter; // [257:162]
362+
csrng_hw2reg_sw_cmd_sts_reg_t sw_cmd_sts; // [161:154]
363+
csrng_hw2reg_genbits_vld_reg_t genbits_vld; // [153:152]
364+
csrng_hw2reg_genbits_reg_t genbits; // [151:120]
365+
csrng_hw2reg_int_state_val_reg_t int_state_val; // [119:88]
366+
csrng_hw2reg_hw_exc_sts_reg_t hw_exc_sts; // [87:71]
367+
csrng_hw2reg_recov_alert_sts_reg_t recov_alert_sts; // [70:53]
368+
csrng_hw2reg_err_code_reg_t err_code; // [52:7]
373369
csrng_hw2reg_main_sm_state_reg_t main_sm_state; // [6:0]
374370
} csrng_hw2reg_t;
375371

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