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[hw,darjeeling] Remove references to 48m clock
Signed-off-by: Robert Schilling <[email protected]>
1 parent ec73b3b commit 7ea60e1

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‎hw/top_darjeeling/ip/ast/README.md‎

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@@ -367,14 +367,6 @@ manager</u></a>.</td>
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<td>aon</td>
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<td>I/O and timer clock enable</td>
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</tr>
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<tr class="even">
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<td>clk_src_io_48m_o</td>
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<td>O</td>
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<td>mubi4</td>
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<td>aon</td>
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<td>Clock frequency indicator. When set, it indicates that the
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clk_src_io_o's frequency is 48 MHz; otherwise, it is 96 MHz.</td>
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</tr>
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<tr class="odd">
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<td colspan="5"><strong>Clock &amp; Reset Inputs</strong></td>
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</tr>

‎hw/top_darjeeling/ip/ast/data/ast_cdc_abstract.sgdc‎

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@@ -451,7 +451,6 @@ abstract_interface_port -name "clk_src_aon_val_o" -definition "output logic clk_
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abstract_interface_port -name "clk_src_io_en_i" -definition "input clk_src_io_en_i; "
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abstract_interface_port -name "clk_src_io_o" -definition "output logic clk_src_io_o; "
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abstract_interface_port -name "clk_src_io_val_o" -definition "output logic clk_src_io_val_o; "
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abstract_interface_port -name "clk_src_io_48m_o" -definition "output prim_mubi_pkg :: mubi4_t clk_src_io_48m_o;"
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abstract_interface_port -name "usb_ref_pulse_i" -definition "input usb_ref_pulse_i; "
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abstract_interface_port -name "usb_ref_val_i" -definition "input usb_ref_val_i; "
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abstract_interface_port -name "clk_src_usb_en_i" -definition "input clk_src_usb_en_i; "
@@ -553,7 +552,6 @@ block_file_decompiled_start
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output -name "clk_src_sys_val_o" -clock "ast.clk_src_sys_o"
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output -name "clk_src_aon_val_o" -clock "ast.clk_src_aon_o"
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output -name "clk_src_io_val_o" -clock "ast.clk_src_io_o"
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output -name "clk_src_io_48m_o" -clock "ast.clk_src_io_o"
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output -name "clk_src_usb_val_o" -clock "ast.clk_src_usb_o"
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output -name "usb_io_pu_cal_o" -clock "ast.clk_ast_tlul_i"
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output -name "rng_val_o" -clock "ast.clk_ast_rng_i"

‎hw/top_darjeeling/ip/ast/rtl/ast.sv‎

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@@ -77,7 +77,6 @@ module ast
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input clk_src_io_en_i, // IO Source Clock Enable
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output logic clk_src_io_o, // IO Source Clock
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output logic clk_src_io_val_o, // IO Source Clock Valid
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output prim_mubi_pkg::mubi4_t clk_src_io_48m_o, // IO Source Clock is 48MHz
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// usb source clock
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input usb_ref_pulse_i, // USB Reference Pulse
@@ -506,7 +505,6 @@ ast_clks_byp u_ast_clks_byp (
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.clk_src_sys_val_o ( clk_src_sys_val_o ),
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.clk_src_io_o ( clk_src_io ),
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.clk_src_io_val_o ( clk_src_io_val_o ),
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.clk_src_io_48m_o ( clk_src_io_48m_o ),
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.clk_src_usb_o ( clk_src_usb ),
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.clk_src_usb_val_o ( clk_src_usb_val_o ),
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.clk_src_aon_o ( clk_src_aon ),
@@ -894,7 +892,6 @@ assign ast2pad_t1_ao = 1'bz;
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`ASSERT_KNOWN(ClkSrcAonValKnownO_A, clk_src_aon_val_o, clk_src_aon_o, rst_aon_clk_n)
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`ASSERT_KNOWN(ClkSrcIoKnownO_A, clk_src_io_o, 1, ast_pwst_o.main_pok)
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`ASSERT_KNOWN(ClkSrcIoValKnownO_A, clk_src_io_val_o, clk_src_io_o, rst_io_clk_n)
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`ASSERT_KNOWN(ClkSrcIo48mKnownO_A, clk_src_io_48m_o, clk_src_io_o, rst_io_clk_n)
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`ASSERT_KNOWN(ClkSrcSysKnownO_A, clk_src_sys_o, 1, ast_pwst_o.main_pok)
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`ASSERT_KNOWN(ClkSrcSysValKnownO_A, clk_src_sys_val_o, clk_src_sys_o, rst_sys_clk_n)
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`ASSERT_KNOWN(ClkSrcUsbKnownO_A, clk_src_usb_o, 1, ast_pwst_o.main_pok)

‎hw/top_darjeeling/ip/ast/rtl/ast_clks_byp.sv‎

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@@ -39,7 +39,6 @@ module ast_clks_byp (
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output logic clk_src_sys_val_o, // SYS Source Clock Valid
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output logic clk_src_io_o, // IO Source Clock
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output logic clk_src_io_val_o, // IO Source Clock Valid
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output prim_mubi_pkg::mubi4_t clk_src_io_48m_o, // IO Source Clock is 48Mhz
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output logic clk_src_usb_o, // USB Source Clock
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output logic clk_src_usb_val_o, // USB Source Clock Valid
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output logic clk_src_aon_o, // AON Source Clock
@@ -742,40 +741,6 @@ prim_mubi4_sender #(
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.mubi_o ( {io_clk_byp_ack_o} )
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);
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// IO Clock Source is 48MHz
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////////////////////////////////////////
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logic io_clk_byp_is_48m_src, io_clk_byp_is_48m;
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// Oscillator source is always 96MHz.
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// External Bypass source is assume to be 96MHz until it is enabled as 48MHz
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always_ff @( posedge clk_aon, negedge rst_aon_n ) begin
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if ( !rst_aon_n ) begin
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io_clk_byp_is_48m_src <= 1'b0;
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end else begin
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io_clk_byp_is_48m_src <= io_clk_byp_en && !ext_freq_is_96m;
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end
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end
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prim_flop_2sync #(
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.Width ( 1 ),
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.ResetValue ( 1'b0 )
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) u_io_clk_byp_is_48m_sync (
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.clk_i ( clk_src_io_o ),
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.rst_ni ( rst_aon_ioda_n ),
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.d_i ( io_clk_byp_is_48m_src ),
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.q_o ( io_clk_byp_is_48m )
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);
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prim_mubi4_sender #(
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.ResetValue ( prim_mubi_pkg::MuBi4False )
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) u_clk_src_io_48m_sync (
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.clk_i ( clk_src_io_o ),
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.rst_ni ( rst_aon_ioda_n ),
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.mubi_i ( prim_mubi_pkg::mubi4_bool_to_mubi(io_clk_byp_is_48m) ),
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.mubi_o ( {clk_src_io_48m_o} )
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);
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/////////////////////
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// Unused Signals //
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/////////////////////

‎hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv‎

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@@ -1333,7 +1333,6 @@ module chip_darjeeling_asic #(
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.clk_src_io_en_i ( base_ast_pwr.io_clk_en ),
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.clk_src_io_o ( ast_base_clks.clk_io ),
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.clk_src_io_val_o ( ast_base_pwr.io_clk_val ),
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.clk_src_io_48m_o ( ),
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// usb source clock
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.usb_ref_pulse_i ( '0 ),
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.usb_ref_val_i ( '0 ),

‎hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv‎

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@@ -1192,7 +1192,6 @@ module chip_darjeeling_cw310 #(
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.clk_src_io_en_i ( base_ast_pwr.io_clk_en ),
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.clk_src_io_o ( ast_base_clks.clk_io ),
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.clk_src_io_val_o ( ast_base_pwr.io_clk_val ),
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.clk_src_io_48m_o ( ),
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// usb source clock
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.usb_ref_pulse_i ( '0 ),
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.usb_ref_val_i ( '0 ),

‎hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv‎

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@@ -516,7 +516,6 @@ module chip_darjeeling_verilator #(
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.clk_src_io_en_i ( base_ast_pwr.io_clk_en ),
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.clk_src_io_o ( ast_base_clks.clk_io ),
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.clk_src_io_val_o ( ast_base_pwr.io_clk_val ),
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.clk_src_io_48m_o ( div_step_down_req ),
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// usb source clock
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.usb_ref_pulse_i ( '0 ),
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.usb_ref_val_i ( '0 ),

‎hw/top_darjeeling/templates/chiplevel.sv.tpl‎

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@@ -706,7 +706,6 @@ module chip_${top["name"]}_${target["name"]} #(
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.clk_src_io_en_i ( base_ast_pwr.io_clk_en ),
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.clk_src_io_o ( ast_base_clks.clk_io ),
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.clk_src_io_val_o ( ast_base_pwr.io_clk_val ),
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.clk_src_io_48m_o ( ),
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// usb source clock
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.usb_ref_pulse_i ( '0 ),
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.usb_ref_val_i ( '0 ),

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