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[hw,darjeeling] Remove references to the flash interface
Signed-off-by: Robert Schilling <[email protected]>
1 parent 06fe280 commit ec73b3b

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10 files changed

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-127
lines changed

10 files changed

+5
-127
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‎hw/top_darjeeling/data/chip_conn_testplan.hjson‎

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -590,19 +590,6 @@
590590
tags: ["conn"]
591591
}
592592

593-
/////////////////////////
594-
// ast_flash.csv //
595-
/////////////////////////
596-
{
597-
name: ast_flash_ctrl
598-
desc: '''Verify ast's flash signals are connected to the flash controller.'''
599-
stage: V2
600-
tests: ["ast_flash_obs_ctrl",
601-
"ast_flash_pwr_dwn_out",
602-
"ast_flash_pwr_rdy_out",
603-
"ast_flash_bist_en_out"]
604-
tags: ["conn"]
605-
}
606593
/////////////////////////////
607594
// ast_csrng_cfg.csv //
608595
/////////////////////////////

‎hw/top_darjeeling/formal/conn_csvs/ast_flash.csv‎

Lines changed: 0 additions & 14 deletions
This file was deleted.

‎hw/top_darjeeling/ip/ast/README.md‎

Lines changed: 0 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -169,22 +169,6 @@ macro.</td>
169169
(<strong>VCC domain</strong>).</td>
170170
</tr>
171171
<tr class="odd">
172-
<td>flash_power_down_h_o</td>
173-
<td>O</td>
174-
<td>1</td>
175-
<td>async</td>
176-
<td>Connected to flash (<strong>VCC domain</strong>). Used for flash
177-
power management.</td>
178-
</tr>
179-
<tr class="even">
180-
<td>flash_power_ready_h_o</td>
181-
<td>O</td>
182-
<td>1</td>
183-
<td>async</td>
184-
<td>Connected to flash (<strong>VCC domain</strong>). Used for flash
185-
power management.</td>
186-
</tr>
187-
<tr class="odd">
188172
<td><p>vcmain_pok</p>
189173
<p>(aka vcmain_pok_o)</p></td>
190174
<td>O</td>
@@ -659,13 +643,6 @@ cycle</u></a>.</p></td>
659643
<td>async</td>
660644
<td>Strap inputs for DFT selection</td>
661645
</tr>
662-
<tr class="even">
663-
<td>flash_bist_en_o</td>
664-
<td>O</td>
665-
<td>mubi4</td>
666-
<td></td>
667-
<td>Flash BIST enable</td>
668-
</tr>
669646
<tr class="odd">
670647
<td>vcc_supp_i</td>
671648
<td>I</td>
@@ -817,13 +794,6 @@ that the external clock is 96MHz.</td>
817794
<td>async</td>
818795
<td><p>DFT enable</p></td>
819796
</tr>
820-
<tr class="odd">
821-
<td>fla_obs_i</td>
822-
<td>I</td>
823-
<td>8</td>
824-
<td>async</td>
825-
<td>Flash observe bus for debug</td>
826-
</tr>
827797
<tr class="even">
828798
<td>otp_obs_i</td>
829799
<td>I</td>
@@ -931,9 +901,6 @@ immediately negated. In addition, SYS clock, IO clock and USB clock are
931901
stopped. This means that negation of the VCC supply always triggers the
932902
flash brown-out (BOR) protection circuitry.
933903

934-
When entering deep-sleep mode, 'flash_power_down_h_o' is
935-
asserted before negating VCMAIN until VCMAIN is back up.
936-
937904
## Resets
938905

939906
The AST supports the generation of the root reset for the reset manager.

‎hw/top_darjeeling/ip/ast/data/ast_cdc_abstract.sgdc‎

Lines changed: 0 additions & 10 deletions
Large diffs are not rendered by default.

‎hw/top_darjeeling/ip/ast/rtl/ast.sv‎

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -60,8 +60,6 @@ module ast
6060
input main_env_iso_en_i, // Enveloped ISOlation ENable for MAIN
6161

6262
// power down monitor logic - flash/otp related
63-
output logic flash_power_down_h_o, // Flash Power Down
64-
output logic flash_power_ready_h_o, // Flash Power Ready
6563
input [1:0] otp_power_seq_i, // MMR0,24 in (VDD)
6664
output logic [1:0] otp_power_seq_h_o, // MMR0,24 masked by PDM, out (VCC)
6765

@@ -101,7 +99,6 @@ module ast
10199

102100
// dft interface
103101
input lc_ctrl_pkg::lc_tx_t lc_dft_en_i, // DFT enable (secure bus)
104-
input [8-1:0] fla_obs_i, // FLASH Observe Bus
105102
input [8-1:0] otp_obs_i, // OTP Observe Bus
106103
input [8-1:0] otm_obs_i, // OT Modules Observe Bus
107104
input usb_obs_i, // USB DIFF RX Observe
@@ -125,7 +122,6 @@ module ast
125122
output prim_mubi_pkg::mubi4_t all_clk_byp_ack_o, // Switch all clocks to External clocks
126123
input prim_mubi_pkg::mubi4_t io_clk_byp_req_i, // IO clock bypass request (for OTP bootstrap)
127124
output prim_mubi_pkg::mubi4_t io_clk_byp_ack_o, // Switch IO clock to External clock
128-
output prim_mubi_pkg::mubi4_t flash_bist_en_o, // Flush BIST (TAP) Enable
129125

130126
// memories read-write margins
131127
output ast_pkg::dpm_rm_t dpram_rmf_o, // Dual Port RAM Read-write Margin Fast
@@ -171,9 +167,6 @@ prim_clock_buf #(
171167
.clk_o ( clk_aon )
172168
);
173169

174-
175-
assign flash_bist_en_o = prim_mubi_pkg::MuBi4False;
176-
//
177170
assign dft_scan_md_o = prim_mubi_pkg::MuBi4False;
178171
assign scan_shift_en_o = 1'b0;
179172
assign scan_reset_no = 1'b1;
@@ -313,8 +306,6 @@ rglts_pdm_3p3v u_rglts_pdm_3p3v (
313306
.vcc_pok_str_h_o ( ast_pwst_h_o.vcc_pok ),
314307
.vcc_pok_str_1p1_h_o ( vcc_pok_str ),
315308
.deep_sleep_h_o ( deep_sleep ),
316-
.flash_power_down_h_o ( flash_power_down_h_o ),
317-
.flash_power_ready_h_o ( flash_power_ready_h_o ),
318309
.otp_power_seq_h_o ( otp_power_seq_h_o[2-1:0] )
319310
);
320311

@@ -930,8 +921,6 @@ assign ast2pad_t1_ao = 1'bz;
930921
`ASSERT_KNOWN(VioaPokHKnownO_A, ast_pwst_h_o.io_pok[0], clk_src_aon_o, por_ni)
931922
`ASSERT_KNOWN(ViobPokHKnownO_A, ast_pwst_h_o.io_pok[1], clk_src_aon_o, por_ni)
932923
// FLASH/OTP
933-
`ASSERT_KNOWN(FlashPowerDownKnownO_A, flash_power_down_h_o, 1, ast_pwst_o.main_pok)
934-
`ASSERT_KNOWN(FlashPowerReadyKnownO_A, flash_power_ready_h_o, 1, ast_pwst_o.main_pok)
935924
`ASSERT_KNOWN(OtpPowerSeqKnownO_A, otp_power_seq_h_o, 1, ast_pwst_o.main_pok)
936925
// Alerts
937926
`ASSERT_KNOWN(AlertReqKnownO_A, alert_req_o, clk_ast_alert_i, rst_ast_alert_ni)
@@ -947,7 +936,6 @@ assign ast2pad_t1_ao = 1'bz;
947936
`ASSERT_KNOWN(DftScanMdKnownO_A, dft_scan_md_o, clk_ast_tlul_i, ast_pwst_o.aon_pok)
948937
`ASSERT_KNOWN(ScanShiftEnKnownO_A, scan_shift_en_o, clk_ast_tlul_i, ast_pwst_o.aon_pok)
949938
`ASSERT_KNOWN(ScanResetKnownO_A, scan_reset_no, clk_ast_tlul_i, ast_pwst_o.aon_pok)
950-
`ASSERT_KNOWN(FlashBistEnKnownO_A, flash_bist_en_o, clk_ast_tlul_i, ast_pwst_o.aon_pok)
951939

952940
// Alert assertions for reg_we onehot check
953941
`ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR(RegWeOnehot_A,
@@ -970,7 +958,6 @@ assign unused_sigs = ^{ clk_ast_usb_i,
970958
rst_vcmpp_aon_n,
971959
padmux2ast_i[Pad2AstInWidth-1:0],
972960
lc_dft_en_i[3:0],
973-
fla_obs_i[8-1:0],
974961
otp_obs_i[8-1:0],
975962
otm_obs_i[8-1:0],
976963
usb_obs_i,

‎hw/top_darjeeling/ip/ast/rtl/rglts_pdm_3p3v.sv‎

Lines changed: 1 addition & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,6 @@ module rglts_pdm_3p3v (
3232
output logic vcc_pok_str_h_o, // VCC Exist Stretched @3.3V
3333
output logic vcc_pok_str_1p1_h_o, // VCC Exist Stretched @3.3V for BE 1.1v (UPF issue)
3434
output logic deep_sleep_h_o, // Deep Sleep (main regulator & switch are off) @3.3v
35-
output logic flash_power_down_h_o, //
36-
output logic flash_power_ready_h_o, //
3735
output logic [2-1:0] otp_power_seq_h_o // MMR0,24 masked by PDM, out (VCC)
3836
);
3937

@@ -47,7 +45,7 @@ assign vio_pok_h_o[1:0] = vio_pok_h_i[1:0]; // Level Up Shifter
4745
///////////////////////////////////////
4846
// Regulators Enable State Machine
4947
///////////////////////////////////////
50-
logic fla_pdm_h, otp_pdm_h;
48+
logic otp_pdm_h;
5149
logic [9-1:0] dly_cnt, hc2lc_val, lc2hc_val; // upto 255 aon clock (1275us)
5250

5351
// DV Hook
@@ -158,7 +156,6 @@ always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin
158156
rglssm_vcmon_h_o <= 1'b0; //
159157
rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
160158
rglssm_brout_h_o <= 1'b0; //
161-
fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT))
162159
//
163160
dly_cnt <= cld_pu_val; // VCMAIN Regulator power-up time
164161
//
@@ -173,7 +170,6 @@ always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin
173170
rglssm_vcmon_h_o <= 1'b0; //
174171
rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
175172
rglssm_brout_h_o <= 1'b0; //
176-
fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON)||(rgls_sm == RGLS_BROUT))
177173
//
178174
dly_cnt <= dly_cnt - 1'b1;
179175
//
@@ -182,7 +178,6 @@ always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin
182178
vcaon_pok_h <= 1'b1; // VCAON Rail Enabled
183179
rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON)
184180
rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
185-
fla_pdm_h <= 1'b0; //
186181
rgls_sm <= RGLS_VCMON; // VCMAIN Regultor is ON!
187182
end else begin
188183
rgls_sm <= RGLS_CLDPU; // Power VCMAIN!
@@ -197,21 +192,18 @@ always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin
197192
rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON)
198193
rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
199194
rglssm_brout_h_o <= 1'b0; //
200-
fla_pdm_h <= 1'b0; //
201195
//
202196
dly_cnt <= hc2lc_val; // VCAON Regulator power-up time
203197
//
204198
if ( !vcc_pok_s_h ) begin
205199
rglssm_vcmon_h_o <= 1'b0; //
206200
rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
207201
rglssm_brout_h_o <= 1'b1; // (rgls_sm == RGLS_BROUT)
208-
fla_pdm_h <= 1'b0; //
209202
rgls_sm <= RGLS_BROUT; // Brownout
210203
end else if ( main_pd_h_i && !por_sync_h_i ) begin
211204
main_pd_str_h <= 1'b1; // Power Down Stretch on
212205
rglssm_vcmon_h_o <= 1'b0; //
213206
rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
214-
fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT))
215207
rgls_sm <= RGLS_VCM2A; // VCMAIN to VCAON Transition
216208
end else begin
217209
rgls_sm <= RGLS_VCMON; // VCMAIN Regulator is ON!
@@ -226,7 +218,6 @@ always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin
226218
rglssm_vcmon_h_o <= 1'b0; //
227219
rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
228220
rglssm_brout_h_o <= 1'b0; //
229-
fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT))
230221
//
231222
dly_cnt <= dly_cnt - 1'b1;
232223
//
@@ -235,7 +226,6 @@ always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin
235226
vcaon_pok_h <= 1'b1; // VCAON Rail Enabled
236227
rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON)
237228
rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
238-
fla_pdm_h <= 1'b0; //
239229
rgls_sm <= RGLS_VCMON; // VCMAIN Regultor is ON!
240230
end else if ( dly_cnt == '0 ) begin
241231
rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
@@ -253,7 +243,6 @@ always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin
253243
rglssm_vcmon_h_o <= 1'b0; //
254244
rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
255245
rglssm_brout_h_o <= 1'b0; //
256-
fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT))
257246
//
258247
dly_cnt <= lc2hc_val; // VCMAIN Regulator power-up time
259248
//
@@ -273,7 +262,6 @@ always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin
273262
rglssm_vcmon_h_o <= 1'b0; //
274263
rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
275264
rglssm_brout_h_o <= 1'b0; //
276-
fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT))
277265
//
278266
dly_cnt <= dly_cnt - 1'b1;
279267
//
@@ -282,7 +270,6 @@ always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin
282270
vcaon_pok_h <= 1'b1; // VCAON Rail Enabled
283271
rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON)
284272
rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
285-
fla_pdm_h <= 1'b0; //
286273
rgls_sm <= RGLS_VCMON; // VCMAIN Regulator is ON!
287274
end else begin
288275
rgls_sm <= RGLS_VCA2M; // VCAON->VCMAIN Transition
@@ -297,7 +284,6 @@ always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin
297284
rglssm_vcmon_h_o <= 1'b0; //
298285
rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
299286
rglssm_brout_h_o <= 1'b1; // (rgls_sm == RGLS_BROUT)
300-
fla_pdm_h <= 1'b0; //
301287
//
302288
dly_cnt <= lc2hc_val; // VCMAIN Regulator power-up time
303289
//
@@ -312,7 +298,6 @@ always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin
312298
rglssm_vcmon_h_o <= 1'b0; //
313299
rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
314300
rglssm_brout_h_o <= 1'b0; //
315-
fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT))
316301
//
317302
dly_cnt <= lc2hc_val; // VCMAIN Regulator power-up time
318303
//
@@ -386,14 +371,6 @@ always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin
386371
end
387372

388373

389-
///////////////////////////////////////
390-
// Flash
391-
///////////////////////////////////////
392-
// fla_pdm_h = !(rglssm_vcmon || rglssm_brout);
393-
assign flash_power_down_h_o = scan_mode_h_i || fla_pdm_h;
394-
assign flash_power_ready_h_o = vcc_pok_h_i;
395-
396-
397374
///////////////////////////////////////
398375
// OTP
399376
///////////////////////////////////////

‎hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1317,9 +1317,7 @@ module chip_darjeeling_asic #(
13171317
// main regulator
13181318
.main_env_iso_en_i ( base_ast_pwr.pwr_clamp_env ),
13191319
.main_pd_ni ( base_ast_pwr.main_pd_n ),
1320-
// pdm control (flash)/otp
1321-
.flash_power_down_h_o ( ),
1322-
.flash_power_ready_h_o ( ),
1320+
// pdm control (otp)
13231321
.otp_power_seq_i ( otp_macro_pwr_seq ),
13241322
.otp_power_seq_h_o ( otp_macro_pwr_seq_h ),
13251323
// system source clock
@@ -1352,7 +1350,6 @@ module chip_darjeeling_asic #(
13521350
.alert_req_o ( ast_alert_req ),
13531351
// dft
13541352
.lc_dft_en_i ( lc_dft_en ),
1355-
.fla_obs_i ( '0 ),
13561353
.usb_obs_i ( '0 ),
13571354
.otp_obs_i ( otp_obs ),
13581355
.otm_obs_i ( '0 ),
@@ -1365,7 +1362,6 @@ module chip_darjeeling_asic #(
13651362
.all_clk_byp_ack_o ( ),
13661363
.io_clk_byp_req_i ( io_clk_byp_req ),
13671364
.io_clk_byp_ack_o ( ),
1368-
.flash_bist_en_o ( ),
13691365
// Memory configuration connections
13701366
.dpram_rmf_o ( ast_ram_2p_fcfg ),
13711367
.dpram_rml_o ( ast_ram_2p_lcfg ),

‎hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1176,9 +1176,7 @@ module chip_darjeeling_cw310 #(
11761176
// main regulator
11771177
.main_env_iso_en_i ( base_ast_pwr.pwr_clamp_env ),
11781178
.main_pd_ni ( base_ast_pwr.main_pd_n ),
1179-
// pdm control (flash)/otp
1180-
.flash_power_down_h_o ( ),
1181-
.flash_power_ready_h_o ( ),
1179+
// pdm control (otp)
11821180
.otp_power_seq_i ( otp_macro_pwr_seq ),
11831181
.otp_power_seq_h_o ( otp_macro_pwr_seq_h ),
11841182
// system source clock
@@ -1211,7 +1209,6 @@ module chip_darjeeling_cw310 #(
12111209
.alert_req_o ( ast_alert_req ),
12121210
// dft
12131211
.lc_dft_en_i ( lc_dft_en ),
1214-
.fla_obs_i ( '0 ),
12151212
.usb_obs_i ( '0 ),
12161213
.otp_obs_i ( otp_obs ),
12171214
.otm_obs_i ( '0 ),
@@ -1224,7 +1221,6 @@ module chip_darjeeling_cw310 #(
12241221
.all_clk_byp_ack_o ( ),
12251222
.io_clk_byp_req_i ( io_clk_byp_req ),
12261223
.io_clk_byp_ack_o ( ),
1227-
.flash_bist_en_o ( ),
12281224
// Memory configuration connections
12291225
.dpram_rmf_o ( ast_ram_2p_fcfg ),
12301226
.dpram_rml_o ( ast_ram_2p_lcfg ),

‎hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -500,9 +500,7 @@ module chip_darjeeling_verilator #(
500500
// main regulator
501501
.main_env_iso_en_i ( base_ast_pwr.pwr_clamp_env ),
502502
.main_pd_ni ( base_ast_pwr.main_pd_n ),
503-
// pdm control (flash)/otp
504-
.flash_power_down_h_o ( ),
505-
.flash_power_ready_h_o ( ),
503+
// pdm control (otp)
506504
.otp_power_seq_i ( otp_macro_pwr_seq ),
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.otp_power_seq_h_o ( otp_macro_pwr_seq_h ),
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// system source clock
@@ -535,7 +533,6 @@ module chip_darjeeling_verilator #(
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.alert_req_o ( ast_alert_req ),
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// dft
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.lc_dft_en_i ( lc_dft_en ),
538-
.fla_obs_i ( '0 ),
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.usb_obs_i ( '0 ),
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.otp_obs_i ( otp_obs ),
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.otm_obs_i ( '0 ),
@@ -548,7 +545,6 @@ module chip_darjeeling_verilator #(
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.all_clk_byp_ack_o ( all_clk_byp_ack ),
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.io_clk_byp_req_i ( io_clk_byp_req ),
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.io_clk_byp_ack_o ( io_clk_byp_ack ),
551-
.flash_bist_en_o ( ),
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// Memory configuration connections
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.dpram_rmf_o ( ),
554550
.dpram_rml_o ( ),

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