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[adc_ctrl,dv] Make start of adc_ctrl_fsm_reset_vseq slightly clearer
No functional change, but it allows the code to avoid a bit of repetition and avoids the reader (me!) getting confused about whether [0] refers to the channel or filter number. Signed-off-by: Rupert Swarbrick <[email protected]>
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hw/ip/adc_ctrl/dv/env/seq_lib/adc_ctrl_fsm_reset_vseq.sv

Lines changed: 27 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -93,23 +93,39 @@ class adc_ctrl_fsm_reset_vseq extends adc_ctrl_base_vseq;
9393
`DV_ASSERT_CTRL_REQ("ADC_CTRL_FSM_A_CTRL", 1)
9494
endtask
9595

96+
function void set_named_field(uvm_reg csr, string name, uvm_reg_data_t value);
97+
uvm_reg_field fld = csr.get_field_by_name(name);
98+
if (!fld) begin
99+
`uvm_fatal(`gfn, $sformatf("Register %s has no field called %s.", csr.get_name(), name))
100+
end
101+
102+
fld.set(value);
103+
endfunction
104+
105+
// Configure the filter whose control register is in csr so that it will match every possible
106+
// input.
107+
task set_filter_to_always_match(uvm_reg csr);
108+
uvm_status_e status;
109+
110+
set_named_field(csr, "min_v", 0);
111+
set_named_field(csr, "max_v", 1023);
112+
set_named_field(csr, "cond", 0);
113+
set_named_field(csr, "en", 1);
114+
csr.update(status);
115+
116+
if (status != UVM_IS_OK) begin
117+
`uvm_error(`gfn, $sformatf("Failed to update filter register (in %s)", csr.get_name()))
118+
end
119+
endtask
96120

97121
virtual task body();
98122
uvm_reg_data_t rdata;
99123
// Make sure ADC is off
100124
csr_wr(ral.adc_en_ctl, 'h0);
101125

102-
// Make sure filters will always match
103-
ral.adc_chn0_filter_ctl[0].min_v.set(0);
104-
ral.adc_chn0_filter_ctl[0].max_v.set(1023);
105-
ral.adc_chn0_filter_ctl[0].cond.set(0);
106-
ral.adc_chn0_filter_ctl[0].en.set(1);
107-
ral.adc_chn1_filter_ctl[0].min_v.set(0);
108-
ral.adc_chn1_filter_ctl[0].max_v.set(1023);
109-
ral.adc_chn1_filter_ctl[0].cond.set(0);
110-
ral.adc_chn1_filter_ctl[0].en.set(1);
111-
csr_wr(ral.adc_chn0_filter_ctl[0], ral.adc_chn0_filter_ctl[0].get());
112-
csr_wr(ral.adc_chn1_filter_ctl[0], ral.adc_chn1_filter_ctl[0].get());
126+
// Make sure ony filter on each channel will always match
127+
set_filter_to_always_match(ral.adc_chn0_filter_ctl[0]);
128+
set_filter_to_always_match(ral.adc_chn1_filter_ctl[0]);
113129

114130
repeat (num_trans) begin
115131
// Set up sample counts

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