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[csrng/rtl] Remove the rcstage FIFO from ctr_drbg_cmd
This commit removes another large FIFO from the data path, measuring about 6kGE. Since the data path bifurcates in ctr_drbg_cmd for all commands that require processing by ctr_drbg_upd, a simple FSM is now required to orchestrate handshaking between the upstream requester, ctr_drbg_upd and the keyvrc FIFO. This step hence also requires the testing of the added sparse-encoded FSM in dv, documentation of this SEC.CM, and a corresponding bit in the ERR_CODE register. Signed-off-by: Florian Glaser <[email protected]>
1 parent 1271c0b commit 9fbd25f

18 files changed

+292
-254
lines changed

‎hw/ip/csrng/data/csrng.hjson‎

Lines changed: 15 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -178,6 +178,9 @@
178178
{ name: "MAIN_SM.FSM.SPARSE"
179179
desc: "The CSRNG main state machine uses a sparse state encoding."
180180
}
181+
{ name: "UPDRSP.FSM.SPARSE"
182+
desc: "The CSRNG update response state machine uses a sparse state encoding."
183+
}
181184
{ name: "UPDATE.FSM.SPARSE"
182185
desc: "The CSRNG update state machine uses a sparse state encoding."
183186
}
@@ -188,13 +191,13 @@
188191
desc: "The CSRNG block output state machine uses a sparse state encoding."
189192
}
190193
{ name: "GEN_CMD.CTR.REDUN"
191-
desc: "The generate command uses a counter that is protected by a second counter that counts in the opposite direction."
194+
desc: "The generate command uses a counter that is protected by a second counter that counts in the opposite direction."
192195
}
193196
{ name: "DRBG_UPD.CTR.REDUN"
194-
desc: "The ctr_drbg update algorithm uses a counter that is protected by a second counter that counts in the opposite direction."
197+
desc: "The ctr_drbg update algorithm uses a counter that is protected by a second counter that counts in the opposite direction."
195198
}
196199
{ name: "DRBG_GEN.CTR.REDUN"
197-
desc: "The ctr_drbg generate algorithm uses a counter that is protected by a second counter that counts in the opposite direction."
200+
desc: "The ctr_drbg generate algorithm uses a counter that is protected by a second counter that counts in the opposite direction."
198201
}
199202
{ name: "CTRL.MUBI"
200203
desc: "Multi-bit field used for selection control."
@@ -728,15 +731,6 @@
728731
This bit will stay set until the next reset.
729732
'''
730733
}
731-
{ bits: "3",
732-
name: "SFIFO_RCSTAGE_ERR",
733-
desc: '''
734-
This bit will be set to one when an error has been detected for the
735-
rcstage FIFO. The type of error is reflected in the type status
736-
bits (bits 28 through 30 of this register).
737-
This bit will stay set until the next reset.
738-
'''
739-
}
740734
{ bits: "4",
741735
name: "SFIFO_KEYVRC_ERR",
742736
desc: '''
@@ -873,6 +867,15 @@
873867
This bit will stay set until the next reset.
874868
'''
875869
}
870+
{ bits: "27",
871+
name: "DRBG_CMD_SM_ERR",
872+
desc: '''
873+
This bit will be set when the state machine in the ctr_drbg_cmd unit has entered
874+
an illegal state.
875+
This error will signal a fatal alert, and also an interrupt, if enabled.
876+
This bit will stay set until the next reset.
877+
'''
878+
}
876879
{ bits: "28",
877880
name: "FIFO_WRITE_ERR",
878881
desc: '''

‎hw/ip/csrng/data/csrng_sec_cm_testplan.hjson‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,17 @@
6666
stage: V2S
6767
tests: ["csrng_sec_cm", "csrng_intr", "csrng_err"]
6868
}
69+
{
70+
name: sec_cm_updrsp_fsm_sparse
71+
desc: '''
72+
Verify the countermeasure(s) UPDRSP.FSM.SPARSE.
73+
The csrng_intr and csrng_err tests verify that if the FSM state is forced to an illegal state encoding 1) this is reported with a cs_fatal_err interrupt in the INTR_STATE register and 2) the corresponding bit in the ERR_CODE register is set.
74+
They currently don't check whether the DUT actually triggers a fatal alert.
75+
Alert connection and triggering are verified through automated FPV.
76+
'''
77+
stage: V2S
78+
tests: ["csrng_sec_cm", "csrng_intr", "csrng_err"]
79+
}
6980
{
7081
name: sec_cm_update_fsm_sparse
7182
desc: '''

‎hw/ip/csrng/doc/interfaces.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,7 @@ Referring to the [Comportable guideline for peripheral device functionality](htt
4343
| CSRNG.CONFIG.MUBI | Registers have multi-bit encoded fields. |
4444
| CSRNG.INTERSIG.MUBI | OTP signal used to enable software access to registers. |
4545
| CSRNG.MAIN_SM.FSM.SPARSE | The CSRNG main state machine uses a sparse state encoding. |
46+
| CSRNG.UPDRSP.FSM.SPARSE | The CSRNG update response state machine uses a sparse state encoding. |
4647
| CSRNG.UPDATE.FSM.SPARSE | The CSRNG update state machine uses a sparse state encoding. |
4748
| CSRNG.BLK_ENC.FSM.SPARSE | The CSRNG block encrypt state machine uses a sparse state encoding. |
4849
| CSRNG.OUTBLK.FSM.SPARSE | The CSRNG block output state machine uses a sparse state encoding. |

‎hw/ip/csrng/doc/registers.md‎

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -555,12 +555,12 @@ Writing a zero resets this status bit.
555555
Hardware detection of error conditions status register
556556
- Offset: `0x54`
557557
- Reset default: `0x0`
558-
- Reset mask: `0x77f0fe1b`
558+
- Reset mask: `0x7ff0fe13`
559559

560560
### Fields
561561

562562
```wavejson
563-
{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_RCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
563+
{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_CMD_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
564564
```
565565

566566
| Bits | Type | Reset | Name |
@@ -569,7 +569,7 @@ Hardware detection of error conditions status register
569569
| 30 | ro | 0x0 | [FIFO_STATE_ERR](#err_code--fifo_state_err) |
570570
| 29 | ro | 0x0 | [FIFO_READ_ERR](#err_code--fifo_read_err) |
571571
| 28 | ro | 0x0 | [FIFO_WRITE_ERR](#err_code--fifo_write_err) |
572-
| 27 | | | Reserved |
572+
| 27 | ro | 0x0 | [DRBG_CMD_SM_ERR](#err_code--drbg_cmd_sm_err) |
573573
| 26 | ro | 0x0 | [CMD_GEN_CNT_ERR](#err_code--cmd_gen_cnt_err) |
574574
| 25 | ro | 0x0 | [AES_CIPHER_SM_ERR](#err_code--aes_cipher_sm_err) |
575575
| 24 | ro | 0x0 | [DRBG_UPDOB_SM_ERR](#err_code--drbg_updob_sm_err) |
@@ -587,8 +587,7 @@ Hardware detection of error conditions status register
587587
| 9 | ro | 0x0 | [SFIFO_FINAL_ERR](#err_code--sfifo_final_err) |
588588
| 8:5 | | | Reserved |
589589
| 4 | ro | 0x0 | [SFIFO_KEYVRC_ERR](#err_code--sfifo_keyvrc_err) |
590-
| 3 | ro | 0x0 | [SFIFO_RCSTAGE_ERR](#err_code--sfifo_rcstage_err) |
591-
| 2 | | | Reserved |
590+
| 3:2 | | | Reserved |
592591
| 1 | ro | 0x0 | [SFIFO_GENBITS_ERR](#err_code--sfifo_genbits_err) |
593592
| 0 | ro | 0x0 | [SFIFO_CMD_ERR](#err_code--sfifo_cmd_err) |
594593

@@ -610,6 +609,12 @@ this register) are asserted as a result of an error pulse generated from
610609
any full FIFO that has been received a write pulse.
611610
This bit will stay set until the next reset.
612611

612+
### ERR_CODE . DRBG_CMD_SM_ERR
613+
This bit will be set when the state machine in the ctr_drbg_cmd unit has entered
614+
an illegal state.
615+
This error will signal a fatal alert, and also an interrupt, if enabled.
616+
This bit will stay set until the next reset.
617+
613618
### ERR_CODE . CMD_GEN_CNT_ERR
614619
This bit will be set to one when a mismatch in any of the hardened counters
615620
has been detected.
@@ -701,12 +706,6 @@ keyvrc FIFO. The type of error is reflected in the type status
701706
bits (bits 28 through 30 of this register).
702707
This bit will stay set until the next reset.
703708

704-
### ERR_CODE . SFIFO_RCSTAGE_ERR
705-
This bit will be set to one when an error has been detected for the
706-
rcstage FIFO. The type of error is reflected in the type status
707-
bits (bits 28 through 30 of this register).
708-
This bit will stay set until the next reset.
709-
710709
### ERR_CODE . SFIFO_GENBITS_ERR
711710
This bit will be set to one when an error has been detected for the
712711
command stage genbits FIFO. The type of error is reflected in the type status

‎hw/ip/csrng/dv/cov/csrng_cov_if.sv‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -243,15 +243,15 @@ interface csrng_cov_if (
243243
// If ERR_CODE register has SFIFO related field set, it also needs to set at least one
244244
// FIFO_*_ERR field.
245245
illegal_bins illegal = !binsof(cp_err_codes) intersect { CMD_STAGE_SM_ERR, MAIN_SM_ERR,
246-
DRBG_GEN_SM_ERR, DRBG_UPDBE_SM_ERR,
247-
DRBG_UPDOB_SM_ERR, AES_CIPHER_SM_ERR,
248-
CMD_GEN_CNT_ERR } &&
249-
binsof(cp_fifo_err_type) intersect { 0 };
246+
DRBG_CMD_SM_ERR, DRBG_GEN_SM_ERR,
247+
DRBG_UPDBE_SM_ERR, DRBG_UPDOB_SM_ERR,
248+
AES_CIPHER_SM_ERR, CMD_GEN_CNT_ERR }
249+
&& binsof(cp_fifo_err_type) intersect { 0 };
250250

251251
ignore_bins ignore = binsof(cp_err_codes) intersect { CMD_STAGE_SM_ERR, MAIN_SM_ERR,
252-
DRBG_GEN_SM_ERR, DRBG_UPDBE_SM_ERR,
253-
DRBG_UPDOB_SM_ERR, AES_CIPHER_SM_ERR,
254-
CMD_GEN_CNT_ERR };
252+
DRBG_CMD_SM_ERR, DRBG_GEN_SM_ERR,
253+
DRBG_UPDBE_SM_ERR, DRBG_UPDOB_SM_ERR,
254+
AES_CIPHER_SM_ERR, CMD_GEN_CNT_ERR };
255255
}
256256

257257
cp_csrng_aes_fsm_err: coverpoint

‎hw/ip/csrng/dv/env/csrng_env_pkg.sv‎

Lines changed: 67 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -53,81 +53,84 @@ package csrng_env_pkg;
5353
invalid_read_int_state = 2
5454
} invalid_mubi_e;
5555

56+
// Keep these in groups and with ascending encodings as the env_cfg refers to
57+
// ranges of certain errors to define the distribution of error codes to test.
5658
typedef enum int {
5759
sfifo_cmd_error = 0,
5860
sfifo_genbits_error = 1,
59-
sfifo_rcstage_error = 3,
60-
sfifo_keyvrc_error = 4,
61-
sfifo_final_error = 9,
62-
sfifo_gbencack_error = 10,
63-
sfifo_grcstage_error = 11,
64-
sfifo_ggenreq_error = 12,
65-
sfifo_gadstage_error = 13,
66-
sfifo_ggenbits_error = 14,
67-
sfifo_cmdid_error = 15,
68-
cmd_stage_sm_error = 16,
69-
main_sm_error = 17,
70-
drbg_gen_sm_error = 18,
71-
drbg_updbe_sm_error = 19,
72-
drbg_updob_sm_error = 20,
73-
aes_cipher_sm_error = 21,
74-
cmd_gen_cnt_error = 22,
75-
fifo_write_error = 23,
76-
fifo_read_error = 24,
77-
fifo_state_error = 25
61+
sfifo_keyvrc_error = 2,
62+
sfifo_final_error = 3,
63+
sfifo_gbencack_error = 4,
64+
sfifo_grcstage_error = 5,
65+
sfifo_ggenreq_error = 6,
66+
sfifo_gadstage_error = 7,
67+
sfifo_ggenbits_error = 8,
68+
sfifo_cmdid_error = 9,
69+
cmd_stage_sm_error = 10,
70+
main_sm_error = 11,
71+
drbg_cmd_sm_error = 12,
72+
drbg_gen_sm_error = 13,
73+
drbg_updbe_sm_error = 14,
74+
drbg_updob_sm_error = 15,
75+
aes_cipher_sm_error = 16,
76+
cmd_gen_cnt_error = 17,
77+
fifo_write_error = 18,
78+
fifo_read_error = 19,
79+
fifo_state_error = 20
7880
} fatal_err_e;
7981

8082
typedef enum int {
8183
// ERR_CODE
8284
sfifo_cmd_err = 0,
8385
sfifo_genbits_err = 1,
84-
sfifo_rcstage_err = 3,
85-
sfifo_keyvrc_err = 4,
86-
sfifo_final_err = 9,
87-
sfifo_gbencack_err = 10,
88-
sfifo_grcstage_err = 11,
89-
sfifo_ggenreq_err = 12,
90-
sfifo_gadstage_err = 13,
91-
sfifo_ggenbits_err = 14,
92-
sfifo_cmdid_err = 15,
93-
cmd_stage_sm_err = 16,
94-
main_sm_err = 17,
95-
drbg_gen_sm_err = 18,
96-
drbg_updbe_sm_err = 19,
97-
drbg_updob_sm_err = 20,
98-
aes_cipher_sm_err = 21,
99-
cmd_gen_cnt_err = 22,
100-
fifo_write_err = 23,
101-
fifo_read_err = 24,
102-
fifo_state_err = 25,
86+
sfifo_keyvrc_err = 2,
87+
sfifo_final_err = 3,
88+
sfifo_gbencack_err = 4,
89+
sfifo_grcstage_err = 5,
90+
sfifo_ggenreq_err = 6,
91+
sfifo_gadstage_err = 7,
92+
sfifo_ggenbits_err = 8,
93+
sfifo_cmdid_err = 9,
94+
cmd_stage_sm_err = 10,
95+
main_sm_err = 11,
96+
drbg_cmd_sm_err = 12,
97+
drbg_gen_sm_err = 13,
98+
drbg_updbe_sm_err = 14,
99+
drbg_updob_sm_err = 15,
100+
aes_cipher_sm_err = 16,
101+
cmd_gen_cnt_err = 17,
102+
fifo_write_err = 18,
103+
fifo_read_err = 19,
104+
fifo_state_err = 20,
103105
// ERR_CODE_TEST
104-
sfifo_cmd_err_test = 26,
105-
sfifo_genbits_err_test = 27,
106-
sfifo_rcstage_err_test = 29,
107-
sfifo_keyvrc_err_test = 30,
108-
sfifo_final_err_test = 35,
109-
sfifo_gbencack_err_test = 36,
110-
sfifo_grcstage_err_test = 37,
111-
sfifo_ggenreq_err_test = 38,
112-
sfifo_gadstage_err_test = 39,
113-
sfifo_ggenbits_err_test = 40,
114-
sfifo_cmdid_err_test = 41,
115-
cmd_stage_sm_err_test = 42,
116-
main_sm_err_test = 43,
117-
drbg_gen_sm_err_test = 44,
118-
drbg_updbe_sm_err_test = 45,
119-
drbg_updob_sm_err_test = 46,
120-
aes_cipher_sm_err_test = 47,
121-
cmd_gen_cnt_err_test = 48,
122-
fifo_write_err_test = 49,
123-
fifo_read_err_test = 50,
124-
fifo_state_err_test = 51
106+
sfifo_cmd_err_test = 21,
107+
sfifo_genbits_err_test = 22,
108+
sfifo_keyvrc_err_test = 23,
109+
sfifo_final_err_test = 24,
110+
sfifo_gbencack_err_test = 25,
111+
sfifo_grcstage_err_test = 26,
112+
sfifo_ggenreq_err_test = 27,
113+
sfifo_gadstage_err_test = 28,
114+
sfifo_ggenbits_err_test = 29,
115+
sfifo_cmdid_err_test = 30,
116+
cmd_stage_sm_err_test = 31,
117+
main_sm_err_test = 32,
118+
drbg_cmd_sm_err_test = 33,
119+
drbg_gen_sm_err_test = 34,
120+
drbg_updbe_sm_err_test = 35,
121+
drbg_updob_sm_err_test = 36,
122+
aes_cipher_sm_err_test = 37,
123+
cmd_gen_cnt_err_test = 38,
124+
fifo_write_err_test = 39,
125+
fifo_read_err_test = 40,
126+
fifo_state_err_test = 41
125127
} err_code_e;
126128

129+
// These encodings must match the respective bit position of each
130+
// field in the regfile/IP hjson.
127131
typedef enum int {
128132
SFIFO_CMD_ERR = 0,
129133
SFIFO_GENBITS_ERR = 1,
130-
SFIFO_RCSTAGE_ERR = 3,
131134
SFIFO_KEYVRC_ERR = 4,
132135
SFIFO_FINAL_ERR = 9,
133136
SFIFO_GBENCACK_ERR = 10,
@@ -143,6 +146,7 @@ package csrng_env_pkg;
143146
DRBG_UPDOB_SM_ERR = 24,
144147
AES_CIPHER_SM_ERR = 25,
145148
CMD_GEN_CNT_ERR = 26,
149+
DRBG_CMD_SM_ERR = 27,
146150
FIFO_WRITE_ERR = 28,
147151
FIFO_READ_ERR = 29,
148152
FIFO_STATE_ERR = 30
@@ -167,10 +171,9 @@ package csrng_env_pkg;
167171
sfifo_grcstage = 4,
168172
sfifo_gbencack = 5,
169173
sfifo_final = 6,
170-
sfifo_keyvrc = 11,
171-
sfifo_rcstage = 12,
172-
sfifo_genbits = 14,
173-
sfifo_cmd = 15
174+
sfifo_keyvrc = 7,
175+
sfifo_genbits = 8,
176+
sfifo_cmd = 9
174177
} which_fifo_e;
175178

176179
typedef enum int {

‎hw/ip/csrng/dv/env/csrng_path_if.sv‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ interface csrng_path_if
1717
case (fifo_name) inside
1818
"sfifo_cmd", "sfifo_genbits": return {core_path, $sformatf(".gen_cmd_stage[%0d]", app),
1919
".u_csrng_cmd_stage.", fifo_name, "_", which_path};
20-
"sfifo_rcstage", "sfifo_keyvrc": return {core_path, ".u_csrng_ctr_drbg_cmd.",
20+
"sfifo_keyvrc": return {core_path, ".u_csrng_ctr_drbg_cmd.",
2121
fifo_name, "_", which_path};
2222
"sfifo_final": return {core_path, ".u_csrng_ctr_drbg_upd.", fifo_name, "_", which_path};
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"sfifo_gbencack", "sfifo_grcstage", "sfifo_ggenreq", "sfifo_gadstage", "sfifo_ggenbits":
@@ -36,6 +36,7 @@ interface csrng_path_if
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"drbg_gen_sm": return {core_path, ".u_csrng_ctr_drbg_gen.state_q"};
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"drbg_updbe_sm": return {core_path, ".u_csrng_ctr_drbg_upd.blk_enc_state_q"};
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"drbg_updob_sm": return {core_path, ".u_csrng_ctr_drbg_upd.outblk_state_q"};
39+
"drbg_cmd_sm": return {core_path, ".u_csrng_ctr_drbg_cmd.state_q"};
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default: `uvm_fatal("csrng_path_if", "Invalid sm name!")
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endcase // case (which_sm)
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endfunction // sm_err_path

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