[verilator,bazel] Move Englishbreakfast to new Verilator Bazel flow

Razer6 · Razer6 · commit d00a6c867ea2 · 2025-10-31T12:31:36.000Z
Signed-off-by: Robert Schilling &lt;rschilling@rivosinc.com&gt;
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -304,8 +304,8 @@ jobs:
           service_account_json: '${{ secrets.BAZEL_CACHE_CREDS }}'
       - name: Build simulator with Verilator
         run: |
-          ./bazelisk.sh build //hw/top_englishbreakfast:verilator_sim
-          sim_binary_path=$(./bazelisk.sh cquery --output=files //hw/top_englishbreakfast:verilator_sim)
+          ./bazelisk.sh build --//hw/top=englishbreakfast //hw:verilator_real
+          sim_binary_path=$(./bazelisk.sh cquery --//hw/top=englishbreakfast --output=files //hw:verilator_real)
           mkdir -p build-bin/hw/top_englishbreakfast
           cp ${sim_binary_path} build-bin/hw/top_englishbreakfast/
       - name: Upload binary
diff --git a/hw/BUILD b/hw/BUILD
@@ -102,7 +102,7 @@ fusesoc_build(
     data = ["//hw/ip/otbn:rtl_files"],
     make_options = ":make_options",
     output_groups = opentitan_select_top_attr("top_verilator_binary"),
-    systems = ["lowrisc:dv:chip_verilator_sim"],
+    systems = opentitan_select_top_attr("top_verilator_core"),
     tags = [
         "manual",
         "verilator",
diff --git a/hw/top_darjeeling/defs.bzl b/hw/top_darjeeling/defs.bzl
@@ -12,6 +12,7 @@ DARJEELING = opentitan_top(
     hjson = "//hw/top_darjeeling/data/autogen:top_darjeeling.gen.hjson",
     top_lib = "//hw/top_darjeeling/sw/autogen:top_darjeeling",
     top_rtl = "//hw/top_darjeeling:rtl_files",
+    top_verilator_core = ["lowrisc:dv:top_darjeeling_chip_verilator_sim"],
     top_verilator_binary = {"binary": ["lowrisc_dv_top_darjeeling_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb"]},
     top_ld = "//hw/top_darjeeling/sw/autogen:top_darjeeling_memory",
     otp_map = "//hw/top_darjeeling/data/otp:otp_ctrl_mmap.hjson",
diff --git a/hw/top_darjeeling/dv/verilator/chip_sim.core b/hw/top_darjeeling/dv/verilator/chip_sim.core
@@ -4,8 +4,6 @@ CAPI=2:
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:top_darjeeling_chip_verilator_sim:0.1"
 description: "Darjeeling toplevel for simulation with Verilator"
-virtual:
-  - lowrisc:dv:chip_verilator_sim
 
 filesets:
   files_sim_verilator:
diff --git a/hw/top_earlgrey/defs.bzl b/hw/top_earlgrey/defs.bzl
@@ -12,6 +12,7 @@ EARLGREY = opentitan_top(
     hjson = "//hw/top_earlgrey/data/autogen:top_earlgrey.gen.hjson",
     top_lib = "//hw/top_earlgrey/sw/autogen:top_earlgrey",
     top_rtl = "//hw/top_earlgrey:rtl_files",
+    top_verilator_core = ["lowrisc:dv:top_earlgrey_chip_verilator_sim"],
     top_verilator_binary = {"binary": ["lowrisc_dv_top_earlgrey_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb"]},
     top_ld = "//hw/top_earlgrey/sw/autogen:top_earlgrey_memory",
     otp_map = "//hw/top_earlgrey/data/otp:otp_ctrl_mmap.hjson",
diff --git a/hw/top_earlgrey/dv/verilator/chip_sim.core b/hw/top_earlgrey/dv/verilator/chip_sim.core
@@ -4,8 +4,6 @@ CAPI=2:
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:top_earlgrey_chip_verilator_sim:0.1"
 description: "Earl Grey toplevel for simulation with Verilator"
-virtual:
-  - lowrisc:dv:chip_verilator_sim
 
 filesets:
   files_sim_verilator:
diff --git a/hw/top_englishbreakfast/BUILD b/hw/top_englishbreakfast/BUILD
@@ -11,47 +11,9 @@ filegroup(
     srcs = glob(
         ["**"],
     ) + [
+        "//hw/top_earlgrey:rtl_files",  # Add Earlgrey RTL files for alert_handler_pkg and top_pkg
+        "//hw/top_englishbreakfast/dv/verilator:all_files",
         "//hw/top_englishbreakfast/ip:rtl_files",
     ],
     visibility = ["//visibility:public"],
 )
-
-fusesoc_build(
-    name = "verilator_sim",
-    srcs = [
-        ":rtl_files",
-        "//hw:dpi_files",
-        "//hw:dv_common_files",
-        "//hw:rtl_files",
-        "//hw:verilator_files",
-    ],
-    cores = [
-        "//hw:cores",
-    ],
-    data = ["//hw/ip/otbn:rtl_files"],
-    make_options = ":make_options",
-    output_groups = opentitan_select_top_attr("top_verilator_binary"),
-    systems = ["lowrisc:systems:chip_englishbreakfast_verilator"],
-    tags = [
-        "manual",
-        "verilator",
-    ],
-    target = "sim",
-    verilator_options = ":verilator_options",
-)
-
-string_list_flag(
-    name = "verilator_options",
-    build_setting_default = [
-        "--threads",
-        "2",
-    ],
-)
-
-string_list_flag(
-    name = "make_options",
-    build_setting_default = [
-        "-j",
-        "2",
-    ],
-)
diff --git a/hw/top_englishbreakfast/bitstream/BUILD b/hw/top_englishbreakfast/bitstream/BUILD
@@ -13,6 +13,7 @@ fusesoc_build(
     testonly = True,
     srcs = [
         "//hw:rtl_files",
+        "//hw/top_earlgrey:rtl_files",  # Add Earlgrey RTL files for alert_handler_pkg and top_pkg
         "//hw/top_englishbreakfast:rtl_files",
     ],
     cores = ["//hw:cores"],
diff --git a/hw/top_englishbreakfast/defs.bzl b/hw/top_englishbreakfast/defs.bzl
@@ -11,7 +11,8 @@ ENGLISHBREAKFAST = opentitan_top(
     hjson = "//hw/top_englishbreakfast/data/autogen:top_englishbreakfast.gen.hjson",
     top_lib = "//hw/top_englishbreakfast/sw/autogen:top_englishbreakfast",
     top_rtl = "//hw/top_englishbreakfast:rtl_files",
-    top_verilator_binary = {"binary": ["lowrisc_systems_chip_englishbreakfast_verilator_0.1/sim-verilator/Vchip_englishbreakfast_verilator"]},
+    top_verilator_core = ["lowrisc:dv:top_englishbreakfast_chip_verilator_sim"],
+    top_verilator_binary = {"binary": ["lowrisc_dv_top_englishbreakfast_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb"]},
     top_ld = "//hw/top_englishbreakfast/sw/autogen:top_englishbreakfast_memory",
     ips = ENGLISHBREAKFAST_IPS,
     secret_cfgs = {
diff --git a/hw/top_englishbreakfast/dv/verilator/BUILD b/hw/top_englishbreakfast/dv/verilator/BUILD
@@ -0,0 +1,10 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+    name = "all_files",
+    srcs = glob(["**"]),
+)
diff --git a/hw/top_englishbreakfast/dv/verilator/chip_sim.core b/hw/top_englishbreakfast/dv/verilator/chip_sim.core
@@ -2,10 +2,11 @@ CAPI=2:
 # Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:systems:chip_englishbreakfast_verilator:0.1"
-description: "English Breakfast toplevel for simulation with Verilator"
+name: "lowrisc:dv:top_englishbreakfast_chip_verilator_sim:0.1"
+description: "English Breakfast chip DV sim target"
+
 filesets:
-  files_sim_verilator:
+  files_dv:
     depend:
       - lowrisc:systems:top_englishbreakfast:0.1
       - lowrisc:dv_dpi_c:uartdpi
@@ -34,8 +35,8 @@ filesets:
       - lowrisc:prim_generic:flash
 
     files:
-      - rtl/chip_englishbreakfast_verilator.sv: { file_type: systemVerilogSource }
-      - chip_englishbreakfast_verilator.cc: { file_type: cppSource }
+      - chip_sim_tb.sv: { file_type: systemVerilogSource }
+      - chip_sim_tb.cc: { file_type: cppSource }
 
 parameters:
   RVFI:
@@ -75,8 +76,8 @@ parameters:
 targets:
   default: &default_target
     filesets:
-      - files_sim_verilator
-    toplevel: chip_englishbreakfast_verilator
+      - files_dv
+    toplevel: chip_sim_tb
 
   sim:
     parameters:
@@ -89,8 +90,8 @@ targets:
       - RV_CORE_IBEX_SIM_SRAM=true
     default_tool: verilator
     filesets:
-      - files_sim_verilator
-    toplevel: chip_englishbreakfast_verilator
+      - files_dv
+    toplevel: chip_sim_tb
     tools:
       verilator:
         mode: cc
@@ -104,7 +105,7 @@ targets:
           - '--trace-params'
           - '--trace-max-array 1024'
           - '--unroll-count 512'
-          - '-CFLAGS "-std=c++17 -Wall -DVM_TRACE_FMT_FST -DVL_USER_STOP -DTOPLEVEL_NAME=chip_englishbreakfast_verilator"'
+          - '-CFLAGS "-std=c++17 -Wall -DVM_TRACE_FMT_FST -DVL_USER_STOP -DTOPLEVEL_NAME=chip_sim_tb"'
           - '-LDFLAGS "-pthread -lutil -lelf"'
           - '-Wall'
           # Execute simulation with four threads by default, which works best
diff --git a/hw/top_englishbreakfast/dv/verilator/chip_sim_tb.cc b/hw/top_englishbreakfast/dv/verilator/chip_sim_tb.cc
@@ -9,15 +9,13 @@
 #include "verilator_sim_ctrl.h"
 
 int main(int argc, char **argv) {
-  chip_englishbreakfast_verilator top;
+  chip_sim_tb top;
   VerilatorMemUtil memutil;
   VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
   simctrl.SetTop(&top, &top.clk_i, &top.rst_ni,
                  VerilatorSimCtrlFlags::ResetPolarityNegative);
 
-  std::string top_scope(
-      "TOP.chip_englishbreakfast_verilator."
-      "top_englishbreakfast");
+  std::string top_scope("TOP.chip_sim_tb.top_englishbreakfast");
   std::string ram1p_adv_scope("u_prim_ram_1p_adv.u_mem");
 
   MemArea rom(top_scope +
diff --git a/hw/top_englishbreakfast/dv/verilator/chip_sim_tb.sv b/hw/top_englishbreakfast/dv/verilator/chip_sim_tb.sv
@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-module chip_englishbreakfast_verilator (
+module chip_sim_tb (
   // Clock and Reset
   input clk_i,
   input rst_ni
@@ -365,4 +365,4 @@ module chip_englishbreakfast_verilator (
   `undef RV_CORE_IBEX
   `undef SIM_SRAM_IF
 
-endmodule : chip_englishbreakfast_verilator
+endmodule : chip_sim_tb
diff --git a/hw/top_englishbreakfast/dv/verilator/verilator_sim_cfg.hjson b/hw/top_englishbreakfast/dv/verilator/verilator_sim_cfg.hjson
diff --git a/hw/top_englishbreakfast/top_englishbreakfast.core b/hw/top_englishbreakfast/top_englishbreakfast.core
