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[earlgrey,dv] Remove bogus dbg device from TopEarlgrey #29617

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fddaec3
[earlgrey,dv] Remove bogus dmi device from TopEarlgrey
rswarbrick Mar 29, 2026
25dadaa
[earlgrey,dv] Remove bogus dbg device from TopEarlgrey
rswarbrick Mar 29, 2026
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8 changes: 0 additions & 8 deletions hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -2424,10 +2424,6 @@
{
hart: 0x40140000
}
dmi:
{
hart: 0x0
}
}
param_decl:
{
Expand Down Expand Up @@ -6509,10 +6505,6 @@
{
hart: 0x41200000
}
dbg:
{
hart: 0x00001000
}
}
generate_dif: false
clock_connections:
Expand Down
4 changes: 0 additions & 4 deletions hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson
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Expand Up @@ -2873,10 +2873,6 @@
{
hart: 0x40140000
}
dmi:
{
hart: 0x0
}
}
memory: {}
param_list:
Expand Down
2 changes: 0 additions & 2 deletions hw/top_earlgrey/data/top_earlgrey.hjson
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Expand Up @@ -453,7 +453,6 @@
reset_connections: {rst_ni: "lc_io_div4", rst_kmac_ni: "lc"},
base_addrs: {
regs: {hart: "0x40140000"},
dmi: {hart: "0x0"}, // DMI is not used in EarlGrey
},
param_decl: {
// NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
Expand Down Expand Up @@ -836,7 +835,6 @@
base_addrs: {
mem: {hart: "0x00010000"},
regs: {hart: "0x41200000"},
dbg: {hart: "0x00001000"}, // Not used in Earlgrey
},
generate_dif: "False"
},
Expand Down
2 changes: 0 additions & 2 deletions hw/top_earlgrey/doc/memory_map.md
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Expand Up @@ -28,7 +28,6 @@ The main address space, shared between the CPU and DM
| otp_ctrl | core | `0x40130000` | `0x1000` | `0x400` | core device on otp_ctrl |
| otp_macro | prim | `0x40138000` | `0x20` | `0x8` | prim device on otp_macro |
| lc_ctrl | regs | `0x40140000` | `0x100` | `0x40` | regs device on lc_ctrl |
| lc_ctrl | dmi | `0x0` | `0x1000` | `0x400` | dmi device on lc_ctrl |
| alert_handler | default | `0x40150000` | `0x800` | `0x200` | alert_handler |
| spi_host0 | default | `0x40300000` | `0x40` | `0x10` | spi_host0 |
| spi_host1 | default | `0x40310000` | `0x40` | `0x10` | spi_host1 |
Expand All @@ -48,7 +47,6 @@ The main address space, shared between the CPU and DM
| flash_ctrl | prim | `0x41008000` | `0x80` | `0x20` | prim device on flash_ctrl |
| rv_dm | regs | `0x41200000` | `0x10` | `0x4` | regs device on rv_dm |
| rv_dm | mem | `0x10000` | `0x1000` | `0x400` | mem device on rv_dm |
| rv_dm | dbg | `0x1000` | `0x200` | `0x80` | dbg device on rv_dm |
| rv_plic | default | `0x48000000` | `0x8000000` | `0x2000000` | rv_plic |
| aes | default | `0x41100000` | `0x100` | `0x40` | aes |
| hmac | default | `0x41110000` | `0x2000` | `0x800` | hmac |
Expand Down
20 changes: 0 additions & 20 deletions hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
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Expand Up @@ -149,16 +149,6 @@ package top_earlgrey_pkg;
*/
parameter int unsigned TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES = 32'h100;

/**
* Peripheral base address for dmi device on lc_ctrl in top earlgrey.
*/
parameter int unsigned TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR = 32'h0;

/**
* Peripheral size in bytes for dmi device on lc_ctrl in top earlgrey.
*/
parameter int unsigned TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES = 32'h1000;

/**
* Peripheral base address for alert_handler in top earlgrey.
*/
Expand Down Expand Up @@ -349,16 +339,6 @@ package top_earlgrey_pkg;
*/
parameter int unsigned TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES = 32'h1000;

/**
* Peripheral base address for dbg device on rv_dm in top earlgrey.
*/
parameter int unsigned TOP_EARLGREY_RV_DM_DBG_BASE_ADDR = 32'h1000;

/**
* Peripheral size in bytes for dbg device on rv_dm in top earlgrey.
*/
parameter int unsigned TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES = 32'h200;

/**
* Peripheral base address for rv_plic in top earlgrey.
*/
Expand Down
28 changes: 0 additions & 28 deletions hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs
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Expand Up @@ -217,20 +217,6 @@ pub const LC_CTRL_REGS_BASE_ADDR: usize = 0x40140000;
/// `LC_CTRL_REGS_BASE_ADDR + LC_CTRL_REGS_SIZE_BYTES`.
pub const LC_CTRL_REGS_SIZE_BYTES: usize = 0x100;

/// Peripheral base address for dmi device on lc_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const LC_CTRL_DMI_BASE_ADDR: usize = 0x0;

/// Peripheral size for dmi device on lc_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #LC_CTRL_DMI_BASE_ADDR and
/// `LC_CTRL_DMI_BASE_ADDR + LC_CTRL_DMI_SIZE_BYTES`.
pub const LC_CTRL_DMI_SIZE_BYTES: usize = 0x1000;

/// Peripheral base address for alert_handler in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
Expand Down Expand Up @@ -497,20 +483,6 @@ pub const RV_DM_MEM_BASE_ADDR: usize = 0x10000;
/// `RV_DM_MEM_BASE_ADDR + RV_DM_MEM_SIZE_BYTES`.
pub const RV_DM_MEM_SIZE_BYTES: usize = 0x1000;

/// Peripheral base address for dbg device on rv_dm in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const RV_DM_DBG_BASE_ADDR: usize = 0x1000;

/// Peripheral size for dbg device on rv_dm in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #RV_DM_DBG_BASE_ADDR and
/// `RV_DM_DBG_BASE_ADDR + RV_DM_DBG_SIZE_BYTES`.
pub const RV_DM_DBG_SIZE_BYTES: usize = 0x200;

/// Peripheral base address for rv_plic in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
Expand Down
36 changes: 0 additions & 36 deletions hw/top_earlgrey/sw/autogen/top_earlgrey.h
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Expand Up @@ -282,24 +282,6 @@ extern "C" {
*/
#define TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES 0x100u

/**
* Peripheral base address for dmi device on lc_ctrl in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
#define TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR 0x0u

/**
* Peripheral size for dmi device on lc_ctrl in top earlgrey.
*
* This is the size (in bytes) of the peripheral's reserved memory area. All
* memory-mapped registers associated with this peripheral should have an
* address between #TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR and
* `TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR + TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES`.
*/
#define TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES 0x1000u

/**
* Peripheral base address for alert_handler in top earlgrey.
*
Expand Down Expand Up @@ -642,24 +624,6 @@ extern "C" {
*/
#define TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES 0x1000u

/**
* Peripheral base address for dbg device on rv_dm in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
#define TOP_EARLGREY_RV_DM_DBG_BASE_ADDR 0x1000u

/**
* Peripheral size for dbg device on rv_dm in top earlgrey.
*
* This is the size (in bytes) of the peripheral's reserved memory area. All
* memory-mapped registers associated with this peripheral should have an
* address between #TOP_EARLGREY_RV_DM_DBG_BASE_ADDR and
* `TOP_EARLGREY_RV_DM_DBG_BASE_ADDR + TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES`.
*/
#define TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES 0x200u

/**
* Peripheral base address for rv_plic in top earlgrey.
*
Expand Down
34 changes: 0 additions & 34 deletions hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
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Original file line number Diff line number Diff line change
Expand Up @@ -304,23 +304,6 @@
* `TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR + TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES`.
*/
#define TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES 0x100
/**
* Peripheral base address for dmi device on lc_ctrl in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
#define TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR 0x0

/**
* Peripheral size for dmi device on lc_ctrl in top earlgrey.
*
* This is the size (in bytes) of the peripheral's reserved memory area. All
* memory-mapped registers associated with this peripheral should have an
* address between #TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR and
* `TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR + TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES`.
*/
#define TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES 0x1000
/**
* Peripheral base address for alert_handler in top earlgrey.
*
Expand Down Expand Up @@ -644,23 +627,6 @@
* `TOP_EARLGREY_RV_DM_MEM_BASE_ADDR + TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES`.
*/
#define TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES 0x1000
/**
* Peripheral base address for dbg device on rv_dm in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
#define TOP_EARLGREY_RV_DM_DBG_BASE_ADDR 0x1000

/**
* Peripheral size for dbg device on rv_dm in top earlgrey.
*
* This is the size (in bytes) of the peripheral's reserved memory area. All
* memory-mapped registers associated with this peripheral should have an
* address between #TOP_EARLGREY_RV_DM_DBG_BASE_ADDR and
* `TOP_EARLGREY_RV_DM_DBG_BASE_ADDR + TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES`.
*/
#define TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES 0x200
/**
* Peripheral base address for rv_plic in top earlgrey.
*
Expand Down
10 changes: 6 additions & 4 deletions util/topgen.py
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Original file line number Diff line number Diff line change
Expand Up @@ -856,10 +856,12 @@ def generate_top_ral(topname: str, top: ConfigT, name_to_block: IpBlocksT,

inst_to_block[inst_name] = block_name
for if_name in block.reg_blocks.keys():
if_addr = {
asid: int(addr, 0)
for (asid, addr) in module["base_addrs"][if_name].items()
}
base_addrs = module["base_addrs"].get(if_name)
if base_addrs is None:
continue

if_addr = {asid: int(addr, 0)
for (asid, addr) in base_addrs.items()}
if_addrs[(inst_name, if_name)] = if_addr

# Top-level may override the mem setting. Store the new type to
Expand Down
90 changes: 67 additions & 23 deletions util/topgen/lib.py
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Expand Up @@ -721,11 +721,29 @@ def is_inst(module: ConfigT) -> bool:
return top_level_mem or top_level_module


def get_base_and_size(name_to_block: IpBlocksT, inst: ConfigT,
ifname: Optional[str]) -> Tuple[int, int]:
def get_base_and_size(block: IpBlock,
inst: ConfigT,
ifname: Optional[str]
) -> Tuple[Dict[str, int], int] | None:
'''Return (base_addrs, size) to describe addresses inst uses on ifname.

It may be that this instance doesn't actually use the interface at all in
the top-level (perhaps because its support for the interface is disabled by
a parameter). If so, return None.

If the instance *does* use the interface, base_addrs is a map from address
space ID to the base address of the block in that address space.

size is the size in bytes that the block uses on the interface named
ifname.
'''

# Check whether the top-level connects up this interface. If not, return
# None.
base_addrs = inst['base_addrs'].get(ifname)
if base_addrs is None:
return None

block = name_to_block.get(inst['type'])
assert block, f"No module named {inst['type']} (coming from instance {inst['name']})"
# If inst is the instantiation of some block, find the register block
# that corresponds to ifname
if rb := block.reg_blocks.get(ifname):
Expand All @@ -739,7 +757,7 @@ def get_base_and_size(name_to_block: IpBlocksT, inst: ConfigT,
'default' if ifname is None else repr(ifname),
inst['name'], block.name))

base_addrs = deepcopy(inst['base_addrs'][ifname])
base_addrs = deepcopy(base_addrs)

for (asid, base_addr) in base_addrs.items():
if isinstance(base_addr, str):
Expand Down Expand Up @@ -981,19 +999,28 @@ def _init_device_regions(self, addr_space):
for inst in self.top['module']:
block = self._name_to_block[inst['type']]
for if_name in block.reg_blocks.keys():
bases_size = get_base_and_size(block, inst, if_name)
if bases_size is None:
# Nothing to do for this interface: it is not used in this
# instance.
continue

bases, size = bases_size
base = bases.get(addr_space)
if base is None:
# Again, nothing to do for this interface: it does not
# define anything mapped into addr_space.
continue

full_if = (inst['name'], if_name)
full_if_name = Name.from_snake_case(full_if[0])
if if_name is not None:
full_if_name += Name.from_snake_case(if_name)

name = full_if_name
base, size = get_base_and_size(self._name_to_block, inst,
if_name)
if addr_space not in base:
continue

region = MemoryRegion(self._top_name, name, addr_space,
base[addr_space], size)
base, size)
device_region[inst['name']].update({if_name: region})

self.device_regions[addr_space] = device_region
Expand Down Expand Up @@ -1039,19 +1066,36 @@ def _init_device_memories(self, addr_space):
device_memories = defaultdict(dict)

for inst in self.top['module']:
if "memory" in inst:
for if_name, val in inst["memory"].items():
base, size = get_base_and_size(self._name_to_block, inst,
if_name)
if addr_space not in base:
continue

full_if_name = Name.from_snake_case(inst['name']) + \
Name.from_snake_case(if_name)
region = MemoryRegion(self._top_name, full_if_name, addr_space,
base[addr_space], size)

device_memories[inst['name']].update({if_name: region})
block = self._name_to_block.get(inst['type'])
if block is None:
raise RuntimeError(f"No block defined for instance "
f"type {inst['type']} (with name "
f"{inst['name']})")

for if_name, val in inst.get("memory", {}).items():
bases_size = get_base_and_size(block, inst, if_name)

# We expect bases_size not to be None. If it is None, then the
# instance defines the memory but doesn't give it a base
# address (which seems unlikely to be right).
if bases_size is None:
raise RuntimeError(f"The instance named {inst['name']} "
f"defines a memory for interface "
f"{if_name}, but doesn't give it a "
f"base address.")

bases, size = bases_size
base = bases.get(addr_space)

if base is None:
continue

full_if_name = Name.from_snake_case(inst['name']) + \
Name.from_snake_case(if_name)
region = MemoryRegion(self._top_name, full_if_name, addr_space,
base, size)

device_memories[inst['name']].update({if_name: region})

self.device_memories[addr_space] = device_memories

Expand Down
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