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[dv] Small tidy-ups in dv_base_reg_field #29630

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[dv] Small tidy-ups in dv_base_reg_field #29630

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9224ebe
[dv] Get rid of dv_base_reg_field::set_original_access
rswarbrick Mar 13, 2025
dc9f37e
[dv] Avoid throwing away result in dv_base_reg_field::set_fld_access
rswarbrick Mar 13, 2025
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19 changes: 9 additions & 10 deletions hw/dv/sv/dv_base_reg/dv_base_reg_field.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,12 @@
//
// base register reg class which will be used to generate the reg field
class dv_base_reg_field extends uvm_reg_field;

// The access value that the field had when it was configured. If the field can be locked, its
// access value might change to "RO". This value can be used to restore the original access on
// reset.
local string m_original_access;

local dv_base_reg_field lockable_flds[$];
local bit is_intr_test_fld;
local uvm_reg_data_t staged_val, committed_val, shadowed_val;
Expand Down Expand Up @@ -83,6 +88,7 @@ class dv_base_reg_field extends uvm_reg_field;
.individually_accessible(individually_accessible));
value.rand_mode(is_rand);
this.mubi_access = mubi_access;
this.m_original_access = access;
is_intr_test_fld = !(uvm_re_match("intr_test*", get_parent().get_name()));
shadowed_val = ~committed_val;
endfunction
Expand Down Expand Up @@ -204,20 +210,13 @@ class dv_base_reg_field extends uvm_reg_field;
get_ro_mask = get_ro_mask << this.get_lsb_pos();
endfunction

virtual function void set_original_access(string access);
if (m_original_access == "") begin
m_original_access = access;
end else begin
`uvm_fatal(`gfn, "register original access can only be written once")
end
endfunction

// Lock the write access to this field.
// This only pertains to a lockable field. It is invoked in the `set_lockable_flds_access()`
// method of its corresponding lock (wen) field.
local function void set_fld_access(bit lock);
if (lock) void'(this.set_access("RO"));
else void'(this.set_access(m_original_access));
string old_access = this.set_access(lock ? "RO" : m_original_access);
// Ignore old_access: it's the previous access setting and will either be RO or
// m_original_access, but we don't need to know it explicitly.
endfunction

// If input is a reg, add all fields under the reg; if input is a field, add the specific field.
Expand Down
35 changes: 0 additions & 35 deletions hw/dv/sv/jtag_agent/jtag_dtm_reg_block.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -50,9 +50,6 @@ class jtag_dtm_reg_bypass extends jtag_dtm_base_reg;
.has_reset(1),
.is_rand(1),
.individually_accessible(0));

bypass.set_original_access("RO");

endfunction : build
endclass : jtag_dtm_reg_bypass

Expand Down Expand Up @@ -86,8 +83,6 @@ class jtag_dtm_reg_idcode extends jtag_dtm_base_reg;
.is_rand(1),
.individually_accessible(0));

rsvd.set_original_access("RO");

// Note: The reset value of manufld must be set based on the design.
manufld = (dv_base_reg_field::type_id::create("manufld"));
manufld.configure(
Expand All @@ -102,8 +97,6 @@ class jtag_dtm_reg_idcode extends jtag_dtm_base_reg;
.is_rand(1),
.individually_accessible(0));

manufld.set_original_access("RO");

// Note: The reset value of partnumber must be set based on the design.
partnumber = (dv_base_reg_field::type_id::create("partnumber"));
partnumber.configure(
Expand All @@ -118,8 +111,6 @@ class jtag_dtm_reg_idcode extends jtag_dtm_base_reg;
.is_rand(1),
.individually_accessible(0));

partnumber.set_original_access("RO");

// Note: The reset value of version must be set based on the design.
version = (dv_base_reg_field::type_id::create("version"));
version.configure(
Expand All @@ -133,9 +124,6 @@ class jtag_dtm_reg_idcode extends jtag_dtm_base_reg;
.has_reset(1),
.is_rand(1),
.individually_accessible(0));

version.set_original_access("RO");

endfunction : build
endclass : jtag_dtm_reg_idcode

Expand Down Expand Up @@ -173,8 +161,6 @@ class jtag_dtm_reg_dtmcs extends jtag_dtm_base_reg;
.is_rand(1),
.individually_accessible(0));

version.set_original_access("RO");

// Note: The reset value of abits must be set based on the design.
abits = (dv_base_reg_field::type_id::create("abits"));
abits.configure(
Expand All @@ -193,8 +179,6 @@ class jtag_dtm_reg_dtmcs extends jtag_dtm_base_reg;
.is_rand(1),
.individually_accessible(0));

abits.set_original_access("RO");

dmistat = (dv_base_reg_field::type_id::create("dmistat"));
dmistat.configure(
.parent(this),
Expand All @@ -208,8 +192,6 @@ class jtag_dtm_reg_dtmcs extends jtag_dtm_base_reg;
.is_rand(1),
.individually_accessible(0));

dmistat.set_original_access("RO");

idle = (dv_base_reg_field::type_id::create("idle"));
idle.configure(
.parent(this),
Expand All @@ -223,8 +205,6 @@ class jtag_dtm_reg_dtmcs extends jtag_dtm_base_reg;
.is_rand(1),
.individually_accessible(0));

idle.set_original_access("RO");

zero0 = (dv_base_reg_field::type_id::create("zero0"));
zero0.configure(
.parent(this),
Expand All @@ -238,8 +218,6 @@ class jtag_dtm_reg_dtmcs extends jtag_dtm_base_reg;
.is_rand(1),
.individually_accessible(0));

zero0.set_original_access("RO");

dmireset = (dv_base_reg_field::type_id::create("dmireset"));
dmireset.configure(
.parent(this),
Expand All @@ -253,8 +231,6 @@ class jtag_dtm_reg_dtmcs extends jtag_dtm_base_reg;
.is_rand(1),
.individually_accessible(0));

dmireset.set_original_access("W1C");

dmihardreset = (dv_base_reg_field::type_id::create("dmihardreset"));
dmihardreset.configure(
.parent(this),
Expand All @@ -268,7 +244,6 @@ class jtag_dtm_reg_dtmcs extends jtag_dtm_base_reg;
.is_rand(1),
.individually_accessible(0));

dmihardreset.set_original_access("W1C");
// Writing 1 to this field will clear the dmi register, causing read-check mismatches.
csr_excl.add_excl(dmihardreset.get_full_name(), CsrExclWrite, CsrNonInitTests);

Expand All @@ -284,9 +259,6 @@ class jtag_dtm_reg_dtmcs extends jtag_dtm_base_reg;
.has_reset(1),
.is_rand(0),
.individually_accessible(0));

zero1.set_original_access("RO");

endfunction : build
endclass : jtag_dtm_reg_dtmcs

Expand Down Expand Up @@ -323,8 +295,6 @@ class jtag_dtm_reg_dmi extends jtag_dtm_base_reg;
.is_rand(1),
.individually_accessible(0));

op.set_original_access("RW");

data = (dv_base_reg_field::type_id::create("data"));
data.configure(
.parent(this),
Expand All @@ -338,8 +308,6 @@ class jtag_dtm_reg_dmi extends jtag_dtm_base_reg;
.is_rand(1),
.individually_accessible(0));

data.set_original_access("RW");

address = (dv_base_reg_field::type_id::create("address"));
address.configure(
.parent(this),
Expand All @@ -356,9 +324,6 @@ class jtag_dtm_reg_dmi extends jtag_dtm_base_reg;
.has_reset(1),
.is_rand(1),
.individually_accessible(0));

address.set_original_access("RW");

endfunction : build

// On reads, we do not want to write the op field.
Expand Down
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