ot_spi_device,ot_spi_host: Bugfix + Refactoring + Passthrough mode implementation

docs/opentitan/ot_darjeeling.md

@@ -34,6 +34,7 @@ Please check out `hw/opentitan/ot_ref.log`
 * SPI data flash (from QEMU upstream w/ fixes)
 * [SPI Host controller](ot_spi_host.md)
   * HW bus config is ignored (SPI mode, speed, ...)
+* [SPI Device](ot_spi_device.md)
 * Timer
 * [UART](ot_uart.md)
   * missing RX timeout, TX break not supported
@@ -67,10 +68,6 @@ Devices in this group implement subset(s) of the real HW.
   * [LC controller](lc_ctrl_dmi.md) can be accessed through JTAG using a DM-TL bridge
   * Escalation is not supported
 * [ROM controller](ot_rom_ctrl.md)
-* [SPI device](ot_spi_device.md)
-  * Flash mode supported
-  * TPM mode supported, but shares a CS with flash/passthrough mode and so cannot be used together
-  * Passthrough mode not supported
 * SRAM controller
   * Initialization and scrambling from OTP key supported
   * Wait for init completion (bus stall) emulated
@@ -136,10 +133,10 @@ generate the `.raw` image files.
 
 Darjeeling emulation supports the following buses:
 
-| **Type** | **Num** | **Usage**                         |
-| -------- | ------- | ----------------------------------|
-| `mtd`    |    0    | [SPI host](ot_spi_host.md)        |
-| `pflash` |    0    | [OTP](ot_otp.md)                  |
+| **Type** | **Num** | **Usage**                                                  |
+| -------- | ------- | -----------------------------------------------------------|
+| `mtd`    |    0    | [SPI host](ot_spi_host.md), [SPI device](ot_spi_device.md) |
+| `pflash` |    0    | [OTP](ot_otp.md)                                           |
 
 ## Tools
 

docs/opentitan/ot_earlgrey.md

@@ -32,6 +32,7 @@
 * SPI data flash (from QEMU upstream w/ fixes)
 * [SPI Host controller](ot_spi_host.md)
   * HW bus config is ignored (SPI mode, speed, ...)
+* [SPI Device](ot_spi_device.md)
 * Timer
 * [UART](ot_uart.md)
   * missing RX timeout, TX break not supported
@@ -59,10 +60,6 @@ Devices in this group implement subset(s) of the real HW.
   * Masking is not supported
 * Lifecycle controller
 * [ROM controller](ot_rom_ctrl.md)
-* [SPI device](ot_spi_device.md)
-  * Flash mode supported
-  * TPM mode supported, but shares a CS with flash/passthrough mode and so cannot be used together
-  * Passthrough mode not supported
 * SRAM controller
   * Initialization and scrambling from OTP key supported
   * Wait for init completion (bus stall) emulated
@@ -127,12 +124,12 @@ generate the `.raw` image files.
 
 EarlGrey emulation supports the following buses:
 
-| **Type** | **Num** | **Usage**                         |
-| -------- | ------- | ----------------------------------|
-| `mtd`    |    0    | [SPI host 0](ot_spi_host.md)      |
-| `mtd`    |    1    | [SPI host 1](ot_spi_host.md)      |
-| `mtd`    |    2    | [Embedded Flash](ot_flash.md)     |
-| `pflash` |    0    | [OTP](ot_otp.md)                  |
+| **Type** | **Num** | **Usage**                                                    |
+| -------- | ------- | -------------------------------------------------------------|
+| `mtd`    |    0    | [SPI host 0](ot_spi_host.md), [SPI device](ot_spi_device.md) |
+| `mtd`    |    1    | [SPI host 1](ot_spi_host.md)                                 |
+| `mtd`    |    2    | [Embedded Flash](ot_flash.md)                                |
+| `pflash` |    0    | [OTP](ot_otp.md)                                             |
 
 ## Tools
 

docs/opentitan/ot_spi_device.md

@@ -2,24 +2,22 @@
 
 ## Supported modes
 
-### FW/Generic mode
-
-This mode is only partially supported, and is being deprecated in real HW, so no further work is
-expected for this mode.
-
 ### Flash mode
 
-This mode is fully supported (to the extend of the understanding of the HW...).
+This mode is fully supported (to the extent of the understanding of the HW...).
 
 ### Passthrough mode
 
-This mode is not yet supported.
+This mode is supported, with minor deficiencies: The two-stage read pipeline, and dummy cycle
+counts of 1 to 7 are not supported as SPI transfers are modelled with byte-granularity (see the
+[CharDev protocol](#spi-device-chardev-protocol)). For commands with 1 to 7 dummy cycles specified,
+the maximum 8 dummy cycles (1 dummy byte) will be used.
 
 ### TPM
 
 This mode is partially supported, TPM commands handled by hw are not supported yet. The CharDev
 protocol doesn't support a distinct chip select for TPM, therefore it is sharing the same CS with
-the other modes. If CS is asserted and TPM is enabled, then it will have priority.
+the other modes. If CS is asserted and TPM is enabled, the TPM will have priority.
 
 ## Connection with a SPI Host
 
@@ -61,7 +59,7 @@ Commands:
 IT is also possible to use [`spidevflash.py`](spidevflash.md) tool to upload a binary using the same
 protocol.
 
-### SPI device CharDev protocol
+### SPI Device CharDev protocol
 
 SPI clock is not emulated, but each byte exchanged over the communication channel represent 8-bit
 SPI data. Dual and Quad lines are not emulated, all communications happen over a regular byte

hw/opentitan/Kconfig

@@ -196,6 +196,7 @@ config OT_SOCDBG_CTRL
 
 config OT_SPI_DEVICE
     bool
+    select OT_SPI_HOST
 
 config OT_SPI_HOST
     bool