hw/riscv: Re-enable opentitan machine#321
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jwnrt merged 2 commits intolowRISC:ot-10.2.0from Feb 3, 2026
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Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
Also enables the new machines by default to match the existing style. Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
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lexbaileylowrisc
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AlexJones0
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Re-enabling this machine to make our fork slightly closer to upstream. Had to revert a commit which switched the SoC's array of harts to a single CPU to be able to use the
riscv_boot_info_initAPI properly.This will also be helpful as we upstream the fork as we'll be adding features to the
opentitanmachine.