Eliminate read access latency of rv_timer

Make the read access latency timer of the rv_timer configurable
by the parent module; support either same cycle (0) or a
single-cycle delay (as before).

Switch to AccessLatency of 0. Since the tlul_adapter_reg always
introduces a cycle delay from accepting a transaction
(a_valid & a_ready) and sending the data (d_valid), there is
already a register delay (storage) on the read data path.

This change should therefore reduce the resource requirements
slightly.

Author: alees24

rtl/system/rv_timer.sv

@@ -10,7 +10,9 @@ module rv_timer #(
   // Bus data width (must be 32)
   parameter int unsigned DataWidth    = 32,
   // Bus address width
-  parameter int unsigned AddressWidth = 32
+  parameter int unsigned AddressWidth = 32,
+  // Number of cycles by which the read data lags the request (must be 0 or 1)
+  parameter int unsigned AccessLatency = 1
 ) (
   input  logic                    clk_i,
   input  logic                    rst_ni,
@@ -45,9 +47,8 @@ module rv_timer #(
   logic [TW-1:0]        mtime_q, mtime_d, mtime_inc;
   logic [TW-1:0]        mtimecmp_q, mtimecmp_d;
   logic                 interrupt_q, interrupt_d;
-  logic                 error_q, error_d;
-  logic [DataWidth-1:0] rdata_q, rdata_d;
-  logic                 rvalid_q;
+  logic                 error_d;
+  logic [DataWidth-1:0] rdata_d;
 
   // Global write enable for all registers
   assign timer_we = timer_req_i & timer_we_i;
@@ -121,31 +122,43 @@ module rv_timer #(
     endcase
   end
 
-  // error_q and rdata_q are only valid when rvalid_q is high
-  always_ff @(posedge clk_i) begin
-    if (timer_req_i) begin
-      rdata_q <= rdata_d;
-      error_q <= error_d;
+  if (AccessLatency == 1) begin : gen_access_latency1
+    logic [DataWidth-1:0] rdata_q;
+    logic error_q;
+    logic rvalid_q;
+
+    // error_q and rdata_q are only valid when rvalid_q is high
+    always_ff @(posedge clk_i) begin
+      if (timer_req_i) begin
+        rdata_q <= rdata_d;
+        error_q <= error_d;
+      end
     end
-  end
 
-  assign timer_rdata_o = rdata_q;
+    assign timer_rdata_o = rdata_q;
 
-  // Read data is always valid one cycle after a request
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      rvalid_q <= 1'b0;
-    end else begin
-      rvalid_q <= timer_req_i;
+    // Read data is always valid one cycle after a request
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) begin
+        rvalid_q <= 1'b0;
+      end else begin
+        rvalid_q <= timer_req_i;
+      end
     end
-  end
 
-  assign timer_rvalid_o = rvalid_q;
-  assign timer_err_o    = error_q;
+    assign timer_rvalid_o = rvalid_q;
+    assign timer_err_o    = error_q;
+  end else begin : gen_access_latency0
+    // Zero cycle latency; other cases caught by assertion below.
+    assign timer_rdata_o  = rdata_d;
+    assign timer_rvalid_o = timer_req_i;
+    assign timer_err_o    = error_d;
+  end
 
   bit [DataWidth-ADDR_OFFSET:0] unused_timer_addr;
   assign  unused_timer_addr = timer_addr_i[DataWidth-1:ADDR_OFFSET-1];
 
   // Assertions
   `ASSERT_INIT(param_legal, DataWidth == 32)
+  `ASSERT_INIT(AllowedLatency_A, AccessLatency inside {0, 1})
 endmodule : rv_timer

rtl/system/sonata_system.sv

@@ -130,6 +130,7 @@ module sonata_system
   localparam int unsigned TotalSpiNum   = SPI_NUM + FixedSpiNum; // The total number of SPI devices
   localparam int unsigned FixedGpioNum  = 1; // Number of GPIO instances that don't pass through the pinmux
   localparam int unsigned TotalGpioNum  = GPIO_NUM + FixedGpioNum; // The total number of GPIO instances
+  localparam int unsigned TAccessLatency = 0; // Cycles of read data latency.
 
   // The number of data bits controlled by each mask bit; since the CPU requires
   // only byte level access, explicitly grouping the data bits makes the inferred
@@ -618,8 +619,8 @@ module sonata_system
   assign device_addr[DbgDev][BusAddrWidth-1:DRegAddrWidth] = tl_ifetch_pkg::ADDR_SPACE_DBG_DEV[BusAddrWidth-1:DRegAddrWidth];
 
   tlul_adapter_reg #(
-    .RegAw            ( TRegAddrWidth ),
-    .AccessLatency    ( 1             )
+    .RegAw            ( TRegAddrWidth  ),
+    .AccessLatency    ( TAccessLatency )
   ) timer_device_adapter (
     .clk_i        (clk_sys_i),
     .rst_ni       (rst_sys_ni),
@@ -1151,8 +1152,9 @@ module sonata_system
 
   // RISC-V timer.
   rv_timer #(
-    .DataWidth    ( BusDataWidth ),
-    .AddressWidth ( BusAddrWidth )
+    .DataWidth    ( BusDataWidth   ),
+    .AddressWidth ( BusAddrWidth   ),
+    .AccessLatency( TAccessLatency )
   ) u_rv_timer (
     .clk_i          (clk_sys_i),
     .rst_ni         (rst_sys_ni),