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CHERIoT debug module integrated#387

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marnovandermaas merged 21 commits intolowRISC:mainfrom
marnovandermaas:cheriot-debug-module
Mar 26, 2025
Merged

CHERIoT debug module integrated#387
marnovandermaas merged 21 commits intolowRISC:mainfrom
marnovandermaas:cheriot-debug-module

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@marnovandermaas marnovandermaas commented Mar 14, 2025

This integrates the CHERIoT debug module into Sonata.

Memory inspection and register inspection work, as well as setting break points.

When trying the "run" command in GDB and asking it to start from the beginning, I get a remote failure reply 'E0E', but I'm hoping this will be solved when using a CHERI-aware LLDB.

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@marnovandermaas marnovandermaas force-pushed the cheriot-debug-module branch 2 times, most recently from c8391fb to d5e339a Compare March 14, 2025 11:53
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elliotb-lowrisc reviewed Mar 17, 2025
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I've not managed to get to the point of testing this yet, but here are a couple of early comments.

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elliotb-lowrisc reviewed Mar 18, 2025
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elliotb-lowrisc commented Mar 19, 2025 •
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I tried building LLDB using the CHERIoT LLVM toolchain, but I'm not sure it's CHERI-aware. It seemed less capable than the RISC-V GDB we have in the nix develop shell, unable to read CSRs and it getting the byte order wrong when reading system info registers. I also don't see much by way of changes in the lldb/ part of the toolchain source. EDIT: note, I am a novice when it comes to debuggers and may have missed something.

@marnovandermaas marnovandermaas marked this pull request as draft March 19, 2025 13:25
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elliotb-lowrisc commented Mar 19, 2025

When trying the "run" command in GDB and asking it to start from the beginning, I get a remote failure reply 'E0E'...

I think I've found the cause of this. I noticed the Verilator sim output an Illegal instruction (hart 0) at PC 0xb0000348: 0x39052023 error when run was issued in GDB. This decodes to a sw x16 0x380(x10) instruction. The key part is that rs2 is set to register 16, which does not exist for CHERIoT Ibex. The debugger doesn't know this, however, as misa is set for RV32I, not RV32E. The run command seemed to work when I tried hacking misa to show the reverse.

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marnovandermaas commented Mar 19, 2025 •
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When trying the "run" command in GDB and asking it to start from the beginning, I get a remote failure reply 'E0E'...

I think I've found the cause of this. I noticed the Verilator sim output an Illegal instruction (hart 0) at PC 0xb0000348: 0x39052023 error when run was issued in GDB. This decodes to a sw x16 0x380(x10) instruction. The key part is that rs2 is set to register 16, which does not exist for CHERIoT Ibex. The debugger doesn't know this, however, as misa is set for RV32I, not RV32E. The run command seemed to work when I tried hacking misa to show the reverse.

Cool, that makes sense! It also means that using a CHERIoT-enabled debugger should help this issue.

@marnovandermaas
CHERIoT debug module patch for test logic
3e4423f 
This patch fixes the test logic inside the CHERIoT debug module TAP.
@marnovandermaas
CHERIoT debug module vendor file added
ae55c33
@marnovandermaas
CHERIoT debug module initial import
058ea9d 
Initialize the vendor directory from the CHERIoT debug module upstream
at revision: 145bc9e2186368ec804aadfe61d21e7cbcbba33c
The upstream repository is located at
github.com/CHERIoT-Platform/cheriot-dbg-module
@marnovandermaas
CHERIoT debug module FuseSoC core file
7ddb842
@marnovandermaas
Debug module added to both crossbars
d5afd54 
The debug module needs to be accessible on both the data and instruction
ports.
@marnovandermaas marnovandermaas marked this pull request as ready for review March 19, 2025 15:48
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elliotb-lowrisc reviewed Mar 20, 2025
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elliotb-lowrisc commented Mar 20, 2025

Ah ha! The instruction cache is the culprit. It's not respecting the mutable nature of instructions loaded from the AbstractCmd part of the debug module memory map. Register load Abstract Commands kept ending up returning the value of misa (and early CSR load) rather than the value of the intended register. Disabling the icache by changing sw/cheri/common/boot.S:62 seemed to finally make breakpoints work as they should (combined with hacked RV32E misa value).

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marnovandermaas commented Mar 21, 2025

@elliotb-lowrisc here's a fix for the MISA issue: lowRISC/sunburst-chip#68

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CHERIoT debug module connected up
230904f 
This commit:
- Regenerates both crossbars and connect up debug module.
- Removes the custom debug reset logic.
- Switches from RISC-V to CHERIoT debug module.
- Adjust Verilator lints.
@marnovandermaas
Pulp debug module removed
9e13265
marnovandermaas and others added 7 commits March 24, 2025 11:20
@marnovandermaas
JTAG DPI TCP server patched to avoid blocking
053395b
@marnovandermaas
JTAG DPI added to vendor file
2664ce4
@marnovandermaas
JTAG DPI instantiated from earlgrey_v1
334212b
@marnovandermaas
JTAG DPI OpenOCD config added
8a4c3b2 
An example of how you would use this is:
$ util/mem_helper.sh load_program -e sw/cheri/build/checks/uart_check -t util/verilator-openocd-cfg.tcl
@marnovandermaas
JTAG DPI connected up in Verilator sim
126549c 
This also includes code to restart the core after reprogramming using
the memory helper script.
@nwf @marnovandermaas
xbar: debug host access to hyperram, system_info
130b417 
With the RTOS mainline gaining some support for code in HyperRAM, it
would be nice to be able to load such images in over OpenOCD without
needing to write code to do bounce buffering.

While here, also give the debug host access to the system_info
peripheral, to provide some more diagnostic information.
@marnovandermaas
Crossbar main regenerated
e085bf8 
This connects the debug host up so that it can also inspect the HyperRAM
and the System information IP.
@marnovandermaas marnovandermaas force-pushed the cheriot-debug-module branch 2 times, most recently from 63841b5 to 347aa3d Compare March 24, 2025 13:57
marnovandermaas and others added 7 commits March 24, 2025 14:37
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Debug module documentation expanded
4a2569a 
Also remove stale sw-debug.md
@marnovandermaas
OpenOCD FPGA GDB configuration added
afcf2fd 
This renames the chip to riscv-cheriot and also adds some additional
configuration for GDB.
@marnovandermaas
Memory helper exit command now overwritable
e7b898e 
This means that you can load a new program into memory and not exit
OpenOCD immediately, for example:
util/mem_helper.sh load_program -e sw/cheri/build/checks/uart_check -x ""
@marnovandermaas
Reuse license details applied to CHERIoT debug mod
0829e5c
@marnovandermaas @elliotb-lowrisc
Release procedure: Update Vivado version
0336cf7 
Synthesis under Vivado 2021.1 is currently not passing timing because of
the debug module being added to the instruction fetch bus. Vivado 2024.1
does pass timing so use this instead.

Co-authored-by: Elliot Baptist <elliot.baptist@lowrisc.org>
@marnovandermaas
Test runner updated for new debug module
0befe5d 
Now that we have a properly functioning debug module, we must start the
core again after loading the image.
@marnovandermaas
Update lowrisc_ibex to lowrisc/cheriot-ibex@158a03
f09d47f 
This commit pulls in the latest changes to the sonata-ibex branch, which
reports RV32E as enabled when running in CHERIoT mode and disables the
instruction cache when in debug mode.

Update code from upstream repository
https://github.com/lowrisc/cheriot-ibex.git to revision
158a03fd338f9a5aa977edbe7452bff67c499e93

Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
elliotb-lowrisc
elliotb-lowrisc approved these changes Mar 26, 2025
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Works for me

@marnovandermaas marnovandermaas merged commit 558d8fd into lowRISC:main Mar 26, 2025
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