HyperRAM clocking scheme, HBMC bring up and W956 simulation model

[alees24]

This PR permits the HyperBus Memory Controller (a.k.a HyperRAM) to be used in simulation with a clocking scheme and timing that much more closely models the HyperRAM activity on the FPGA board. More importantly it makes possible the development and testing in simulation of improved HyperRAM access.

• Modify the simulator control test bench to support multiple clocks of different frequencies and phases; the HBMC requires three different clock signals, having specific phase relationships, and all of a different frequency from the Sonata system clock. This change also permits better modelling of the USB connectivity.
• Introduce build switches USE_SEPARATED_CLOCKS and USE_HYPERRAM_SIM_MODEL which must be presented to both the C++ test bench and the SystemVerilog design; see sonata.core.
• Model the Xilinx primitives used in the HBMC implementation. These models are not complete but work well enough for the vendored HBMC design to be simulated without any source modification.
• Add a model of the HyperRAM W956D8 device used on the Sonata FPGA board.

The existing HyperRAM tests all pass with either the SRAM model (USE_HYPERRAM_SIM_MODEL) - as before - or the HBMC-controlled W956 simulation model. To test the latter the following patch may be applied, since the sonata.core file has been set up to preserve the earlier behaviour and favour faster simulations:

--- a/sonata.core
+++ b/sonata.core
@@ -173,7 +173,7 @@ targets:
           - '--trace-structs'
           - '--trace-params'
           - '--trace-max-array 1024'
-          - '-CFLAGS "-Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=top_verilator -DUSE_HYPERRAM_SIM_MODEL"'
+          - '-CFLAGS "-Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=top_verilator -DUSE_SEPARATED_CLOCKS"'
           # Add "-DUSE_SEPARATED_CLOCKS" to CFLAGS for a more accurate simulation.
           - '-LDFLAGS "-pthread -lutil -lelf"'
           - "-Wall"
@@ -182,9 +182,8 @@ targets:
           # Verilator without increasing the unroll count (see Verilator#1266)
           - "--unroll-count 72"
     parameters:
-      - USE_SEPARATED_CLOCKS=false
+      - USE_SEPARATED_CLOCKS=true
       - PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric
-      - USE_HYPERRAM_SIM_MODEL=true
 
   lint:
     <<: *default_target

[elliotb-lowrisc]

I think something isn't quite right with the vendoring at present. Calling util/vendor.py vendor/lowrisc_ibex.vendor.hjson results in the changes of the first commit being reverted. Perhaps the patch needs to be moved up into sonata-system from lowrisc_ibex or to the source lowrisc/cheriot-ibex repository.

I haven't looked at the rest yet I'm afraid.

[elliotb-lowrisc]

I think this looks good. I've some suggestions but nothing major