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Merged
alees24 merged 1 commit into from
Jul 30, 2025
Merged

Dual-ported, buffered interface to HyperBus Memory Controller #439

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6 changes: 5 additions & 1 deletion dv/verilator/sonata_system.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -16,9 +16,13 @@
SonataSystem::SonataSystem(const char *ram_hier_path, int ram_size_words,
const char *hyperram_hier_path, int hyperram_size_words)
: _ram(ram_hier_path, ram_size_words, 4),
#ifdef USE_HYPERRAM_SIM_MODEL
#ifdef USE_HYPERRAM_SRAM_MODEL
// The SRAM model within the `hyperram` IP block is 32 bits wide to
// match the TL-UL bus.
_hyperram(hyperram_hier_path, hyperram_size_words, 4) {}
#else
// The simulation model of the W956 HyperRAM chip employs a memory
// that is 16 bits wide, as per the HyperBus protocol.
_hyperram(hyperram_hier_path, hyperram_size_words / 2, 2) {}
#endif

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4 changes: 2 additions & 2 deletions dv/verilator/sonata_system_main.cc
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Expand Up @@ -8,9 +8,9 @@ int main(int argc, char **argv) {
SonataSystem sonata_system(
"TOP.top_verilator.u_sonata_system.u_sram_top.u_ram.gen_generic.u_impl_generic",
32 * 1024, // 32k words = 128 KiB
#ifdef USE_HYPERRAM_SIM_MODEL
#ifdef USE_HYPERRAM_SRAM_MODEL
// Simple SRAM model used within the Sonata System for faster simulations.
"TOP.top_verilator.u_sonata_system.u_hyperram.u_hyperram_model.u_ram.gen_generic.u_impl_generic",
"TOP.top_verilator.u_sonata_system.u_hyperram.gen_dual_port.u_hyperram_model.u_ram.gen_generic.u_impl_generic",
#else
// HyperRAM simulation model external to the Sonata System; driven by HBMC.
"TOP.top_verilator.u_hyperram_W956.u_ram.gen_generic.u_impl_generic",
Expand Down
4 changes: 3 additions & 1 deletion dv/verilator/sonata_verilator_lint.vlt
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Expand Up @@ -106,9 +106,11 @@ lint_off -rule WIDTHTRUNC -file "*hbmc_iobuf.v"
lint_off -rule UNUSED -file "*hbmc_clk_obuf.v"
lint_off -rule UNUSED -file "*hbmc_iobuf.v"

lint_off -rule UNOPTFLAT -file "*hbmc_tl_top.sv"
lint_off -rule UNOPTFLAT -file "*hbmc_tl_port.sv"
lint_off -rule UNUSED -file "*hbmc_tl_top.sv"

lint_off -rule MULTIDRIVEN -file "*prim_arbiter_fixed.sv"

// Disable warnings in models of FPGA primitives.
lint_off -rule UNUSED -file "*IOBUF.v"
lint_off -rule UNUSED -file "*ISERDESE2.v"
Expand Down
19 changes: 17 additions & 2 deletions dv/verilator/top_verilator.sv
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Expand Up @@ -177,15 +177,15 @@ module top_verilator #(
wire unused_io_ = ^{mb1, ah_tmpio10, rph_g18, rph_g17,
rph_g16_ce2, rph_g8_ce0, rph_g7_ce1,
usrLed};

`ifndef TARGET_XL_BOARD
// HyperRAM interface.
wire [7:0] hyperram_dq;
wire hyperram_rwds;
wire hyperram_ckp;
wire hyperram_ckn;
wire hyperram_nrst;
wire hyperram_cs;

`endif
// Reporting of CHERI enable/disable and any exceptions that occur.
wire [CheriErrWidth-1:0] cheri_err;
logic [CheriErrWidth-1:0] cheri_errored;
Expand Down Expand Up @@ -356,11 +356,16 @@ module top_verilator #(
.clk_usb_i (clk_usb),
.rst_usb_ni (rst_usb_n),

// HyperRAM clocks and reset
`ifdef TARGET_XL_BOARD
// No HyperRAM on Sonata XL
`else
// Hyperram clocks
.clk_hr_i (clk_hr),
.clk_hr90p_i (clk_hr90p),
.clk_hr3x_i (clk_hr3x),
.rst_hr_ni (rst_hr_n),
`endif

.gp_i ({
15'b0,
Expand Down Expand Up @@ -430,12 +435,16 @@ module top_verilator #(

.rgbled_dout_o (),

`ifdef TARGET_XL_BOARD
// No HyperRAM on Sonata XL
`else
.hyperram_dq (hyperram_dq),
.hyperram_rwds (hyperram_rwds),
.hyperram_ckp (hyperram_ckp),
.hyperram_ckn (hyperram_ckn),
.hyperram_nrst (hyperram_nrst),
.hyperram_cs (hyperram_cs),
`endif

.rs485_tx_enable_o(rs485_tx_enable),
.rs485_rx_enable_o(rs485_rx_enable),
Expand Down Expand Up @@ -663,6 +672,11 @@ module top_verilator #(
.rx_i (rs485_uartdpi_rx)
);

`ifdef TARGET_XL_BOARD
// No HyperRAM on Sonata XL
logic unused_hr;
assign unused_hr = ^{clk_hr, clk_hr90p, clk_hr3x, rst_hr_n};
`else
// HyperRAM model (based on W956D8MBYA5I).
hyperram_W956 u_hyperram_W956 (
// Asynchronous reset signal.
Expand All @@ -677,6 +691,7 @@ module top_verilator #(
// Bidirectional data bus.
.dq (hyperram_dq)
);
`endif

export "DPI-C" function mhpmcounter_get;

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3 changes: 3 additions & 0 deletions rtl/ip/hyperram/hyperram.core
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,9 @@ filesets:
- open_hbmc:hyperram:controller
files:
- rtl/hyperram.sv
- rtl/hyperram_rdbuf.sv
- rtl/hyperram_wrbuf.sv
- rtl/hbmc_tl_port.sv
- rtl/hbmc_tl_top.sv
file_type: systemVerilogSource

Expand Down
26 changes: 13 additions & 13 deletions rtl/ip/hyperram/rtl/hbmc_dfifo.sv
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Expand Up @@ -2,16 +2,16 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

// Reimplementation of hbmc_dfifo using OpenTitan primitives, only works for DATA_WIDTH == 32
module hbmc_dfifo #
(
parameter integer DATA_WIDTH = 32
)
(
// Reimplementation of hbmc_dfifo using OpenTitan primitives, only works for DataWidth == 32

module hbmc_dfifo #(
parameter int unsigned DataWidth = 32, // Width of data words, bits.
parameter int unsigned FIFODepth = 8 // Depth of FIFO, entries.
) (
input wire fifo_wr_clk,
input wire fifo_wr_nrst,
input wire [DATA_WIDTH - 1:0] fifo_wr_din,
input wire [DATA_WIDTH/8 - 1:0] fifo_wr_strb,
input wire [DataWidth - 1:0] fifo_wr_din,
input wire [DataWidth/8 - 1:0] fifo_wr_strb,
input wire fifo_wr_ena,
output wire fifo_wr_full,

Expand All @@ -22,8 +22,8 @@ module hbmc_dfifo #
input wire fifo_rd_ena,
output wire fifo_rd_empty
);
// FIFO contains 32-bit data word and 4-bit strobes
localparam int unsigned FIFOWidth = DATA_WIDTH + 4;
// FIFO contains 32-bit data word and 4 bit strobes
localparam int unsigned FIFOWidth = DataWidth + (DataWidth / 8);

logic [FIFOWidth-1:0] fifo_wdata, fifo_rdata;
logic fifo_wready, fifo_rvalid, fifo_rready;
Expand All @@ -35,7 +35,7 @@ module hbmc_dfifo #

prim_fifo_async #(
.Width(FIFOWidth),
.Depth(4)
.Depth(FIFODepth)
) u_fifo (
.clk_wr_i(fifo_wr_clk),
.rst_wr_ni(fifo_wr_nrst),
Expand Down Expand Up @@ -65,8 +65,8 @@ module hbmc_dfifo #
end

initial begin
if (DATA_WIDTH != 32) begin
$fatal("hbmc_dfifo only supports DATA_WIDTH of 32");
if (DataWidth != 32) begin
$fatal("hbmc_dfifo only supports DataWidth of 32");
end
end
endmodule
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