Increase HyperRAM clock frequency #440
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elliotb-lowrisc
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Looks good to me
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Adjust the clock frequency to 200MHz as per the W956 datasheet. The OpenHBMC controller synthesises and operates fine at 200MHz, with the ISERDES operating at 600MHz. Presumably the lower frequency was set conservatively, but now that the HyperRAM interface is capable of bursting and buffering, performance does benefit from the higher frequency. FPGA builds have been soak testing HyperRAM tests for over 12 hours without encountering any faults.
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This PR builds on #439 and depends upon it.
Increase the HyperRAM clock frequency to 200MHz.
Adjust the clock frequency to 200MHz as per the W956 datasheet.
The OpenHBMC controller synthesises and operates fine at 200MHz, with the ISERDES operating at 600MHz. Presumably the lower frequency was set conservatively, but now that the HyperRAM interface is capable of bursting and buffering, performance does benefit from the higher frequency.
FPGA builds have been soak testing HyperRAM tests for over 12 hours without encountering any faults.