Top-level UART redux

hw/top_chip/dv/env/seq_lib/top_chip_dv_pattgen_vseq.sv

@@ -59,10 +59,6 @@ class top_chip_dv_pattgen_vseq extends top_chip_dv_base_vseq;
   task body();
     bit[7:0] byte_arr[];
     super.body();
-
-    // Prevent pattgen_monitor from starting immediately after reset
-    p_sequencer.cfg.m_pattgen_agent_cfg.en_monitor = 0;
-
     // Wait for reset to be asserted and de-asserted before trying to set
     // config parameters, otherwise they may be reset too.
     p_sequencer.ifs.peri_clk_if.wait_for_reset();

hw/top_chip/dv/env/seq_lib/top_chip_dv_uart_base_vseq.sv

@@ -6,7 +6,13 @@ class top_chip_dv_uart_base_vseq extends top_chip_dv_base_vseq;
   `uvm_object_utils(top_chip_dv_uart_base_vseq)
   `uvm_object_new
 
-  int uart_idx;
+  uart_agent_pkg::baud_rate_e uart_baud_rate = uart_agent_pkg::BaudRate1p5Mbps;
+
+  rand int uart_idx;
+
+  constraint uart_idx_c {
+    uart_idx inside {[0:NUarts-1]};
+  }
 
   // Local queue for holding received UART TX data.
   byte uart_tx_data_q[$];
@@ -35,7 +41,7 @@ class top_chip_dv_uart_base_vseq extends top_chip_dv_base_vseq;
                                              bit enable_rx_monitor = 1'b0,
                                              bit en_parity = 1'b0,
                                              bit odd_parity = 1'b0,
-                                             baud_rate_e baud_rate = BaudRate1Mbps);
+                                             baud_rate_e baud_rate = uart_baud_rate);
     if (enable) begin
       `uvm_info(`gfn, $sformatf("Configuring and connecting UART%0d", uart_idx), UVM_LOW)
      p_sequencer.cfg.m_uart_agent_cfgs[uart_idx].set_parity(en_parity, odd_parity);
@@ -68,8 +74,6 @@ class top_chip_dv_uart_base_vseq extends top_chip_dv_base_vseq;
     // config parameters, otherwise they may be reset too.
     p_sequencer.ifs.peri_clk_if.wait_for_reset();
 
-    // `DV_WAIT(cfg.sw_test_status_vif.sw_test_status == SwTestStatusInTest);
-
     configure_uart_agent(.uart_idx(uart_idx), .enable(1), .enable_rx_monitor(1));
   endtask
 

hw/top_chip/dv/env/seq_lib/top_chip_dv_uart_rand_baudrate_vseq.sv

@@ -0,0 +1,81 @@
+// Copyright lowRISC contributors (Sunburst project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`define CALC_NCO(baud_rate, nco_width, clk_freq_khz) \
+  (baud_rate == BaudRate1p5Mbps && clk_freq_khz == 24_000) ? 16'hffff : \
+      (longint'(baud_rate) * (2**(nco_width+4))) / (clk_freq_khz * 1000)
+
+class top_chip_dv_uart_rand_baudrate_vseq extends top_chip_dv_uart_tx_rx_vseq;
+  // import top_chip_system_pkg::PeriClkFreq;
+  `uvm_object_utils(top_chip_dv_uart_rand_baudrate_vseq)
+  `uvm_object_new
+
+  localparam NCO_WIDTH = 16;
+
+  int uart_clk_freq_khz;  // Use khz to avoid fractional value.
+
+  rand baud_rate_e baud_rate;
+
+  constraint baud_rate_c {
+    // constrain nco not over nco width
+    `CALC_NCO(baud_rate, NCO_WIDTH, uart_clk_freq_khz) < (1 << NCO_WIDTH);
+    // only test 4 other speeds, <= 115k is slow which may take a few hours to complete the test
+    baud_rate > BaudRate115200;
+  }
+
+  function void pre_randomize();
+    super.pre_randomize();
+
+    // if (cfg.chip_clock_source != ChipClockSourceInternal) begin
+    //   // Uart bus clock is in div4 domain
+    //   uart_clk_freq_khz = cfg.chip_clock_source * 1000 / 4;  // div4
+    //   if (cfg.chip_clock_source == ChipClockSourceExternal48Mhz) begin
+    //     uart_clk_freq_khz = uart_clk_freq_khz * 2;  // div2
+    //   end
+    // end else begin
+      // internal uart clock
+      uart_clk_freq_khz = top_chip_system_pkg::PeriClkFreq / 1000;
+    // end
+  endfunction
+
+  function void post_randomize();
+    super.post_randomize();
+    uart_baud_rate = baud_rate;
+  endfunction
+
+  virtual task body();
+    // sw_symbol_backdoor_overwrite takes an array as the input
+    bit [7:0] uart_freq_arr[8] = {<<byte{uart_baud_rate}};
+
+    sw_symbol_backdoor_overwrite("kUartBaudrate", uart_freq_arr);
+    `uvm_info(`gfn, $sformatf(
+              "Backdoor_overwrite: configure uart core clk %0d khz, baud_rate: %s",
+              uart_clk_freq_khz,
+              baud_rate.name
+              ), UVM_LOW)
+
+    // if (cfg.chip_clock_source != ChipClockSourceInternal) begin
+    //   bit [7:0] use_extclk_arr[] = {cfg.chip_clock_source != ChipClockSourceInternal};
+    //   bit [7:0] low_speed_sel_arr[] = {cfg.chip_clock_source == ChipClockSourceExternal48Mhz};
+    //   bit [7:0] uart_clk_freq_arr[8] = {<<byte{uart_clk_freq_khz * 1000}};
+
+    //   sw_symbol_backdoor_overwrite("kUseExtClk", use_extclk_arr);
+    //   sw_symbol_backdoor_overwrite("kUseLowSpeedSel", low_speed_sel_arr);
+    //   sw_symbol_backdoor_overwrite("kClockFreqPeripheralHz", uart_clk_freq_arr);
+    // end
+
+    super.body();
+  endtask
+
+  // // When uart starts to send RX data, check if AST is using extclk if extclk is selected.
+  // virtual task send_uart_rx_data(int instance_num, int size = -1, bit random = 0);
+  //   if (cfg.chip_clock_source != ChipClockSourceInternal) begin
+  //     `DV_CHECK(cfg.ast_ext_clk_vif.is_ext_clk_in_use(),
+  //               "expected the external clock to be used for io");
+  //   end
+  //   super.send_uart_rx_data(instance_num, size, random);
+  // endtask
+
+endclass : top_chip_dv_uart_rand_baudrate_vseq
+`undef CALC_NCO

hw/top_chip/dv/env/seq_lib/top_chip_dv_uart_tx_rx_vseq.sv

@@ -27,7 +27,7 @@ class top_chip_dv_uart_tx_rx_vseq extends top_chip_dv_uart_base_vseq;
     super.body();
 
     // Override software constants with randomised data
-    sw_symbol_backdoor_overwrite("kUartIdxDV", uart_idx_data);
+    sw_symbol_backdoor_overwrite("kUartIdxDv", uart_idx_data);
     sw_symbol_backdoor_overwrite("kUartTxData", exp_uart_tx_data);
     sw_symbol_backdoor_overwrite("kExpUartRxData", uart_rx_data);
 

hw/top_chip/dv/env/seq_lib/top_chip_dv_vseq_list.sv

@@ -7,3 +7,4 @@
 `include "top_chip_dv_pattgen_vseq.sv"
 `include "top_chip_dv_uart_base_vseq.sv"
 `include "top_chip_dv_uart_tx_rx_vseq.sv"
+`include "top_chip_dv_uart_rand_baudrate_vseq.sv"

hw/top_chip/dv/env/top_chip_dv_env.core

@@ -30,6 +30,7 @@ filesets:
       - seq_lib/top_chip_dv_pattgen_vseq.sv: {is_include_file: true}
       - seq_lib/top_chip_dv_uart_base_vseq.sv: {is_include_file: true}
       - seq_lib/top_chip_dv_uart_tx_rx_vseq.sv: {is_include_file: true}
+      - seq_lib/top_chip_dv_uart_rand_baudrate_vseq.sv: {is_include_file: true}
     file_type: systemVerilogSource
 
 targets:

hw/top_chip/dv/env/top_chip_dv_env_cfg.sv

@@ -27,12 +27,17 @@ class top_chip_dv_env_cfg extends uvm_object;
     // create pattgen agent config obj
     m_pattgen_agent_cfg = pattgen_agent_cfg::type_id::create("m_pattgen_agent_cfg");
     m_pattgen_agent_cfg.if_mode = Device;
+    // Configuration is required to perform meaningful monitoring
+    m_pattgen_agent_cfg.en_monitor = 0;
 
     // create uart agent config obj
     foreach (m_uart_agent_cfgs[i]) begin
       m_uart_agent_cfgs[i] = uart_agent_cfg::type_id::create($sformatf("m_uart_agent_cfg%0d", i));
       // Do not create uart agent fcov in chip level test.
       m_uart_agent_cfgs[i].en_cov = 0;
+      // Configuration is required to perform meaningful monitoring
+      m_uart_agent_cfgs[i].en_tx_monitor = 0;
+      m_uart_agent_cfgs[i].en_rx_monitor = 0;
     end
   endfunction
 

hw/top_chip/dv/tb/tb.sv

@@ -355,7 +355,7 @@ module top_chip_asic_tb;
   ) u_uartdpi0 (
     .clk_i(u_dut.clk_peri),
     .rst_ni(u_dut.rst_peri_n),
-    .active(1'b1),
+    .active(!uart_if[0].enable),
     .tx_o(uart0_rx_dpi),
     .rx_i(!uart_if[0].enable ? IO60 : 1'bz)
   );

hw/top_chip/dv/top_chip_sim_cfg.hjson

@@ -59,20 +59,19 @@
       run_opts: ["+ChipMemSRAM_image_file={proj_root}/sw/device/build/tests/pattgen_ios_test.vmem"]
     }
     {
-      name: top_uart_smoke
-      uvm_test_seq: top_chip_dv_base_vseq
-      run_opts: ["+ChipMemSRAM_image_file={proj_root}/scratch_sw/bare_metal/build/checks/uart_smoke_check.vmem"]
+      name: uart_baud_rate_test
+      uvm_test_seq: top_chip_dv_uart_rand_baudrate_vseq
+      run_opts: ["+ChipMemSRAM_image_file={proj_root}/sw/device/build/tests/uart_tx_rx_test.vmem"]
     }
     {
-      name: top_uart_tx_rx
-      uvm_test_seq: top_chip_dv_uart_tx_rx_vseq
-      run_opts: ["+ChipMemSRAM_image_file={proj_root}/scratch_sw/bare_metal/build/checks/uart_tx_rx_check.vmem",
-                 "+uart_idx=0"]
+      name: uart_smoketest
+      uvm_test_seq: top_chip_dv_base_vseq
+      run_opts: ["+ChipMemSRAM_image_file={proj_root}/sw/device/build/tests/uart_smoketest.vmem"]
     }
     {
-      name: top_usbdev_smoke
-      uvm_test_seq: top_chip_dv_base_vseq
-      run_opts: ["+ChipMemSRAM_image_file={proj_root}/scratch_sw/bare_metal/build/checks/usbdev_check.vmem"]
+      name: uart_tx_rx_test
+      uvm_test_seq: top_chip_dv_uart_tx_rx_vseq
+      run_opts: ["+ChipMemSRAM_image_file={proj_root}/sw/device/build/tests/uart_tx_rx_test.vmem"]
     }
     {
       name: usbdev_config_host_test
@@ -135,7 +134,11 @@
   regressions: [
     {
       name: smoke
-      tests: ["top_chip_smoke", "pattgen_ios_test", "top_uart_smoke", "top_usbdev_smoke"]
+      tests: ["top_chip_smoke", "pattgen_ios_test", "uart_smoketest", "top_usbdev_smoke"]
+    }
+    {
+      name: uart
+      tests: ["uart_baud_rate_test", "uart_smoketest", "uart_tx_rx_test"]
     }
   ]
 }

hw/top_chip/sw/autogen/top_chip.c

@@ -15,34 +15,34 @@
 const top_chip_plic_peripheral_t
     top_chip_plic_interrupt_for_peripheral[32] = {
   [kTopChipPlicIrqIdNone] = kTopChipPlicPeripheralUnknown,
-  [1] = kTopChipPlicPeripheralUnknown,
+  [kTopChipPlicIrqHwRevoker] = kTopChipPlicPeripheralUnknown,
   [2] = kTopChipPlicPeripheralUnknown,
-  [3] = kTopChipPlicPeripheralUnknown,
+  [kTopChipPlicIrqIdUsbdev] = kTopChipPlicPeripheralUsbdev,
   [4] = kTopChipPlicPeripheralUnknown,
   [5] = kTopChipPlicPeripheralUnknown,
-  [6] = kTopChipPlicPeripheralUnknown,
-  [7] = kTopChipPlicPeripheralUnknown,
-  [8] = kTopChipPlicPeripheralUnknown,
-  [9] = kTopChipPlicPeripheralUnknown,
+  [kTopChipPlicIrqIdPattgen] = kTopChipPlicPeripheralPattgen,
+  [kTopChipPlicIrqIdAonTimer] = kTopChipPlicPeripheralAonTimerAon,
+  [kTopChipPlicIrqIdUart0] = kTopChipPlicPeripheralUart0,
+  [kTopChipPlicIrqIdUart1] = kTopChipPlicPeripheralUart1,
   [10] = kTopChipPlicPeripheralUnknown,
   [11] = kTopChipPlicPeripheralUnknown,
   [12] = kTopChipPlicPeripheralUnknown,
   [13] = kTopChipPlicPeripheralUnknown,
   [14] = kTopChipPlicPeripheralUnknown,
   [15] = kTopChipPlicPeripheralUnknown,
-  [16] = kTopChipPlicPeripheralUnknown,
-  [17] = kTopChipPlicPeripheralUnknown,
+  [kTopChipPlicIrqIdI2c0] = kTopChipPlicPeripheralI2c0,
+  [kTopChipPlicIrqIdI2c1] = kTopChipPlicPeripheralI2c1,
   [18] = kTopChipPlicPeripheralUnknown,
   [19] = kTopChipPlicPeripheralUnknown,
   [20] = kTopChipPlicPeripheralUnknown,
   [21] = kTopChipPlicPeripheralUnknown,
   [22] = kTopChipPlicPeripheralUnknown,
   [23] = kTopChipPlicPeripheralUnknown,
-  [24] = kTopChipPlicPeripheralUnknown,
-  [25] = kTopChipPlicPeripheralUnknown,
+  [kTopChipPlicIrqIdSpiHost0] = kTopChipPlicPeripheralSpiHost0,
+  [kTopChipPlicIrqIdSpiHost1] = kTopChipPlicPeripheralSpiHost1,
   [26] = kTopChipPlicPeripheralUnknown,
   [27] = kTopChipPlicPeripheralUnknown,
-  [28] = kTopChipPlicPeripheralUnknown,
+  [kTopChipPlicIrqIdGpio] = kTopChipPlicPeripheralGpio,
   [29] = kTopChipPlicPeripheralUnknown,
   [30] = kTopChipPlicPeripheralUnknown,
   [31] = kTopChipPlicPeripheralUnknown,

hw/top_chip/sw/autogen/top_chip.h

@@ -49,7 +49,7 @@ extern "C" {
  * This should be used with #mmio_region_from_addr to access the memory-mapped
  * registers associated with the peripheral (usually via a DIF).
  */
-#define TOP_CHIP_UART1_BASE_ADDR 0x40010000u
+#define TOP_CHIP_UART1_BASE_ADDR 0x40301000u
 
 /**
  * Peripheral size for uart1 in top chip.
@@ -211,7 +211,7 @@ extern "C" {
  * This should be used with #mmio_region_from_addr to access the memory-mapped
  * registers associated with the peripheral (usually via a DIF).
  */
-#define TOP_CHIP_PWRMGR_AON_BASE_ADDR 0x40400000u
+// #define TOP_CHIP_PWRMGR_AON_BASE_ADDR 0x40400000u
 
 /**
  * Peripheral size for pwrmgr_aon in top chip.
@@ -229,7 +229,7 @@ extern "C" {
  * This should be used with #mmio_region_from_addr to access the memory-mapped
  * registers associated with the peripheral (usually via a DIF).
  */
-#define TOP_CHIP_RSTMGR_AON_BASE_ADDR 0x40410000u
+// #define TOP_CHIP_RSTMGR_AON_BASE_ADDR 0x40410000u
 
 /**
  * Peripheral size for rstmgr_aon in top chip.
@@ -247,7 +247,7 @@ extern "C" {
  * This should be used with #mmio_region_from_addr to access the memory-mapped
  * registers associated with the peripheral (usually via a DIF).
  */
-#define TOP_CHIP_CLKMGR_AON_BASE_ADDR 0x40420000u
+// #define TOP_CHIP_CLKMGR_AON_BASE_ADDR 0x40420000u
 
 /**
  * Peripheral size for clkmgr_aon in top chip.
@@ -265,7 +265,7 @@ extern "C" {
  * This should be used with #mmio_region_from_addr to access the memory-mapped
  * registers associated with the peripheral (usually via a DIF).
  */
-#define TOP_CHIP_SYSRST_CTRL_AON_BASE_ADDR 0x40430000u
+// #define TOP_CHIP_SYSRST_CTRL_AON_BASE_ADDR 0x40430000u
 
 /**
  * Peripheral size for sysrst_ctrl_aon in top chip.
@@ -337,7 +337,7 @@ extern "C" {
  * This should be used with #mmio_region_from_addr to access the memory-mapped
  * registers associated with the peripheral (usually via a DIF).
  */
-#define TOP_CHIP_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000u
+// #define TOP_CHIP_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000u
 
 /**
  * Peripheral size for regs device on sram_ctrl_ret_aon in top chip.
@@ -355,7 +355,7 @@ extern "C" {
  * This should be used with #mmio_region_from_addr to access the memory-mapped
  * registers associated with the peripheral (usually via a DIF).
  */
-#define TOP_CHIP_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000u
+// #define TOP_CHIP_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000u
 
 /**
  * Peripheral size for ram device on sram_ctrl_ret_aon in top chip.
@@ -479,7 +479,7 @@ extern "C" {
 /**
  * Memory base address for ram_ret_aon in top chip.
  */
-#define TOP_CHIP_RAM_RET_AON_BASE_ADDR 0x40600000u
+// #define TOP_CHIP_RAM_RET_AON_BASE_ADDR 0x40600000u
 
 /**
  * Memory size for ram_ret_aon in top chip.

sw/device/lib/runtime/irq.c

@@ -14,13 +14,10 @@ void irq_set_vector_offset(uintptr_t address) {
   CSR_WRITE(CSR_REG_MTVEC, (uint32_t)address);
 }
 
-void irq_global_ctrl(bool en) {
-  if (en) {
-    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-  } else {
-    CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-  }
-}
+// Global interrupt enable function has been inlined to work around CHERIoT
+// interrupt-disabling backward sentries being used to return from functions.
+// See irq.h for inline definition of:
+// void irq_global_ctrl(bool en);
 
 void irq_external_ctrl(bool en) {
   const uint32_t mask = 1 << IRQ_EXT_ENABLE_OFFSET;

sw/device/lib/runtime/irq.h

@@ -8,6 +8,8 @@
 #include <stdbool.h>
 #include <stdint.h>
 
+#include "sw/device/lib/base/csr.h"
+
 /**
  * Update to the location of vectors as specificed in the linker file
  *
@@ -18,7 +20,15 @@ void irq_set_vector_offset(uintptr_t address);
 /**
  * Enable / disable ibex globlal interrupts
  */
-void irq_global_ctrl(bool en);
+// Global interrupt enable function has been inlined to work around CHERIoT
+// interrupt-disabling backward sentries being used to return from functions.
+inline void irq_global_ctrl(bool en) {
+  if (en) {
+    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+  } else {
+    CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+  }
+}
 
 /**
  * Enable / disable ibex external interrupts

sw/device/tests/CMakeLists.txt

@@ -23,8 +23,7 @@ set(TESTS
   uart_loopback_test.c
   uart_parity_break_test.c
   uart_smoketest.c
-# Needs (dif_)clkmgr:
-#  uart_tx_rx_test.c
+  uart_tx_rx_test.c
   usbdev_config_host_test.c
   usbdev_iso_test.c
   usbdev_mem_test.c