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Merged
elliotb-lowrisc merged 3 commits into from
Mar 3, 2025
Merged

Top-level test set tweaks #53

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9495dc8
[dv] Reintroduce accidentally-deleted USB test
elliotb-lowrisc Feb 27, 2025
e51dd73
[dv] Add `usbdev` regression test set
elliotb-lowrisc Feb 27, 2025
d4f7c61
[doc] Mention how to run all tests
elliotb-lowrisc Feb 27, 2025
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14 changes: 12 additions & 2 deletions README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -159,7 +159,7 @@ It must have already been compiled using the instructions in the [Test software

### Build & run

The `smoke` regression test set (defined in top_chip_sim_cfg.hjson) can be built and run under Xcellium using the following commands:
The **`smoke` regression test set** (defined in top_chip_sim_cfg.hjson) can be built and run under Xcellium using the following commands:

```sh
# -- Build and run top-level `smoke` regression set using Xcelium --
Expand All @@ -169,7 +169,7 @@ The `smoke` regression test set (defined in top_chip_sim_cfg.hjson) can be built
./hw/vendor/lowrisc_ip/util/dvsim/dvsim.py ./hw/top_chip/dv/top_chip_sim_cfg.hjson -i smoke
```

Single tests (also defined in top_chip_sim_cfg.hjson) can be specified in the same way, such as `usbdev_vbus_test`:
**Single tests** (also defined in top_chip_sim_cfg.hjson) can be specified in the same way, such as `usbdev_vbus_test`:

```sh
# -- Build and run the `usbdev_vbus_test` top-level test using Xcelium --
Expand All @@ -182,6 +182,16 @@ Single tests (also defined in top_chip_sim_cfg.hjson) can be specified in the sa
You can **increase the number of times each test is run** using the `-rx <multiplier>` option.
For example, `... -i smoke -rx 10` to run the `smoke` regression set 10 times.

**All tests** can be built and run simply by specifying `all` instead of a regression set or test name:

```sh
# -- Build and run all top-level tests 10 times using Xcelium --
# Run from the project root directory.
# NOTE: test software must have already been built beforehand and Xcelium
# must be available on your path.
./hw/vendor/lowrisc_ip/util/dvsim/dvsim.py ./hw/top_chip/dv/top_chip_sim_cfg.hjson -i all -rx 10
```

### Output

DVSim provides an overall regression report at the end, which should report the number of tests that passed and failed.
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13 changes: 13 additions & 0 deletions hw/top_chip/dv/top_chip_sim_cfg.hjson
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Expand Up @@ -73,6 +73,11 @@
uvm_test_seq: top_chip_dv_uart_tx_rx_vseq
run_opts: ["+ChipMemSRAM_image_file={proj_root}/sw/device/build/tests/uart_tx_rx_test.vmem"]
}
{
name: top_usbdev_smoke
uvm_test_seq: top_chip_dv_base_vseq
run_opts: ["+ChipMemSRAM_image_file={proj_root}/scratch_sw/bare_metal/build/checks/usbdev_check.vmem"]
}
{
name: usbdev_config_host_test
uvm_test_seq: top_chip_dv_base_vseq
Expand Down Expand Up @@ -140,5 +145,13 @@
name: uart
tests: ["uart_baud_rate_test", "uart_smoketest", "uart_tx_rx_test"]
}
{
name: usbdev
tests: [
"top_usbdev_smoke", "usbdev_config_host_test", "usbdev_iso_test", "usbdev_mem_test",
"usbdev_mixed_test", "usbdev_pincfg_test", "usbdev_pullup_test", "usbdev_setuprx_test",
"usbdev_stream_test", "usbdev_test", "usbdev_toggle_restore_test", "usbdev_vbus_test"
]
}
]
}