Use CHERIoT-Platform's debug module

hw/vendor/cheriot-debug-module.lock.hjson

@@ -8,7 +8,7 @@
 {
   upstream:
   {
-    url: https://github.com/SamuelRiedel/riscv-dbg.git
-    rev: c2991e163a21c2142fba79d316fdb5423e3503e2
+    url: https://github.com/CHERIoT-Platform/cheriot-dbg-module.git
+    rev: 845f74ce6deb8e811f695c8dab1e6b4ba9cf2fbd
   }
 }

hw/vendor/cheriot-debug-module.vendor.hjson

@@ -6,7 +6,7 @@
   target_dir: "cheriot_debug_module",
   patch_dir: "patches/cheriot_debug_module",
   upstream: {
-    url: "https://github.com/SamuelRiedel/riscv-dbg.git",
-    rev: "cheriot-rebased",
+    url: "https://github.com/CHERIoT-Platform/cheriot-dbg-module.git",
+    rev: "main",
   }
 }

hw/vendor/cheriot_debug_module/Bender.yml

@@ -10,7 +10,7 @@ package:
 
 dependencies:
   tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 }
-  common_cells: {git: "https://github.com/pulp-platform/common_cells.git", version: 1.24.0}
+  common_cells: {git: https://github.com/pulp-platform/common_cells.git, version: 1.21.0}
 
 sources:
   files:

hw/vendor/cheriot_debug_module/CHANGELOG.md

@@ -4,60 +4,10 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
 and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
 
-## Unreleased
-
-## [0.8.1] - 2023-10-01
-### Changed
-- debug_rom: Add rst
-
-## [0.8.0] - 2023-04-05
-### Fixed
-- dm_csrs: Fix W1C behavior of `sberror` (#155) [@andreaskurth](https://github.com/andreaskurth)
-- gen_rom.py: Port to python3 (#152) [@andreaskurth](https://github.com/andreaskurth)
-
-### Added
-- `xprop_off` to Xprop-incompatible processes (#151) [@andreaskurth](https://github.com/andreaskurth)
-
-## [0.7.0] - 2022-11-02
-### Fixed
-- 64-bit unaligned accesses (#145) [@creinwar](https://github.com/creinwar)
-- Various minor testbench fixes (#146)
-
-### Changed
-- Halted, Resume and Exception addresses are now aligned to 8 bytes
-
-## [0.6.0] - 2022-10-11
-### Fixed
-- Testbench build (#141, #142)
-- remote_bitbang tb build for newer GCC versions (#133) [@epsilon537](https://github.com/noytzach)
-- 32-bit access to abstract data (#27) [@Silabs-ArjanB](https://github.com/Silabs-ArjanB)
-- `dm_mem`: Clear state of hart upon ndmreset (#140) [@andreaskurth](https://github.com/andreaskurth)
-- `dmi_jtag_tap`: Bring all state to initial value in test-logic-reset (#139) [@andreaskurth](https://github.com/andreaskurth)
-- Fix DMI response when command or SBA are busy (#138) [@andreaskurth](https://github.com/andreaskurth)
-
-### Changed
-- Add expontential backoff to read_dmi in tb (#134) [@colluca](https://github.com/colluca)
-
-## [0.5.1] - 2022-04-12
-### Fixed
-- Fixed dmi_bscane_tap top-level signals
-
-## [0.5.0] - 2022-04-04
+## [Unreleased]
 ### Added
-- Add sbaccess8 and sbaccess16 support (#106) [@noytzach](https://github.com/noytzach)
-- Implement SBA bad address error (#12) [@msfchaffner](https://github.com/msfschaffner)
-- Added random reset tests to dmi testbench.
 ### Changed
-- Implement `dmihardreset` functionaliy in `dtmcs` register.
-- `dmi_rst_ni` of `dm_top` is now a synchronous signal. However, `dmi_rst_no` of
-  `dmi_jtag` is glitch-free and asserted during all forms (functional or POR) of
-  resets.
 ### Fixed
-- Fixed documentation (csr)
-- Fixed reset value of sbcs register (#127) [@msfchaffner](https://github.com/msfschaffner)
-- Fixed various ascent lint warnings [@msfchaffner](https://github.com/msfschaffner)
-- Implement proper CDC flushing behavior on functional resets and JTAG resets (asynchronous or TestLogicReset driven).
-- Fix JTAG non-compliance in TestLogicReset state (IR should reset to IDCODE).
 
 ## [0.4.1] - 2021-05-04
 ### Added

hw/vendor/cheriot_debug_module/ci/veri-run-openocd-compliance.sh

@@ -0,0 +1,33 @@
+#!/usr/bin/env bash
+
+set -e
+
+ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
+
+if [ -z "${RISCV}" ]
+then
+    echo "RISCV is empty"
+    exit 1
+fi
+
+
+veri_out=$(mktemp)
+openocd_out=openocd.log
+
+make -C "${ROOT}"/tb veri-run |& tee "${veri_out}"&
+# record veri pid/pgid to kill it if it survives this script
+veri_pid=$!
+veri_pgid=$(ps -o pgid= ${veri_pid} | grep -o [0-9]*)
+
+# block until we get "Listening on port" so that we are safe to connect openocd
+coproc grep -m 1 "Listening on port"
+tail -f -n0 "${veri_out}" --pid "$COPROC_PID" >&"${COPROC[1]}"
+
+echo "Starting openocd"
+"${RISCV}"/bin/openocd -f "${ROOT}"/tb/dm_compliance_test.cfg |& tee "${openocd_out}"
+
+if grep -q "ALL TESTS PASSED" "${openocd_out}"; then
+    exit 0
+fi
+exit 1
+

hw/vendor/cheriot_debug_module/debug_rom/Makefile

@@ -1,7 +1,7 @@
 # See LICENSE.SiFive for license details
 
-#  Conversion to CHERIoT Ibex ISA from RISC-V
-#  Copyright SCI Semiconductor 2025
+## Conversion to CHERIoT Ibex ISA from RISC-V
+##   Copyright SCI Semiconductor 2025
 
 debug_rom = debug_rom.sv debug_rom.dump
 
@@ -10,7 +10,7 @@ OBJCOPY=${CHERIOT_LLVM_ROOT}/llvm-objcopy
 OBJDUMP=${CHERIOT_LLVM_ROOT}/llvm-objdump
 LD=${CHERIOT_LLVM_ROOT}/ld.lld
 
-PYTHON?=python3
+PYTHON?=python
 
 all: $(debug_rom)
 

hw/vendor/cheriot_debug_module/debug_rom/debug_rom.S

@@ -9,9 +9,9 @@
 // # define SND_SCRATCH 1
 // These are implementation-specific addresses in the Debug Module
 #define HALTED    0x100
-#define GOING     0x108
-#define RESUMING  0x110
-#define EXCEPTION 0x118
+#define GOING     0x104
+#define RESUMING  0x108
+#define EXCEPTION 0x10C
 
 // Region of memory where each hart has 1
 // byte to read.

hw/vendor/cheriot_debug_module/debug_rom/debug_rom.dump

@@ -38,20 +38,20 @@ Disassembly of section .text:
      854: 17 05 00 00  	auipcc	ca0, 0
      858: 13 55 c5 00  	srli	a0, a0, 12
      85c: 13 15 c5 00  	slli	a0, a0, 12
-     860: 23 2c 05 10  	csw	zero, 280(ca0)
+     860: 23 26 05 10  	csw	zero, 268(ca0)
      864: 5b 05 a0 03  	cspecialr	ca0, 26
      868: 5b 04 90 03  	cspecialr	cs0, 25
      86c: 73 00 10 00  	ebreak
 
 00000870 <going>:
-     870: 23 24 05 10  	csw	zero, 264(ca0)
+     870: 23 22 05 10  	csw	zero, 260(ca0)
      874: 5b 05 a0 03  	cspecialr	ca0, 26
      878: 5b 04 90 03  	cspecialr	cs0, 25
      87c: 6f f0 5f a8  	j	0x300 <whereto>
 
 00000880 <_resume>:
      880: 73 24 40 f1  	csrr	s0, mhartid
-     884: 23 28 85 10  	csw	s0, 272(ca0)
+     884: 23 24 85 10  	csw	s0, 264(ca0)
      888: 5b 05 a0 03  	cspecialr	ca0, 26
      88c: 5b 04 90 03  	cspecialr	cs0, 25
      890: 73 00 20 7b  	dret

hw/vendor/cheriot_debug_module/debug_rom/debug_rom.h

@@ -27,16 +27,16 @@ uint32_t reset_vec[reset_vec_size] = {
     0x00000517,
     0x00c55513,
     0x00c51513,
-    0x10052c23,
+    0x10052623,
     0x03a0055b,
     0x0390045b,
     0x00100073,
-    0x10052423,
+    0x10052223,
     0x03a0055b,
     0x0390045b,
     0xa85ff06f,
     0xf1402473,
-    0x10852823,
+    0x10852423,
     0x03a0055b,
     0x0390045b,
     0x7b200073,

hw/vendor/cheriot_debug_module/debug_rom/debug_rom.sv

@@ -20,7 +20,6 @@
 // Auto-generated code
 module debug_rom (
   input  logic         clk_i,
-  input  logic         rst_ni,
   input  logic         req_i,
   input  logic [63:0]  addr_i,
   output logic [63:0]  rdata_o
@@ -32,11 +31,11 @@ module debug_rom (
   assign mem = {
     64'h00000000_7b200073,
     64'h0390045b_03a0055b,
-    64'h10852823_f1402473,
+    64'h10852423_f1402473,
     64'ha85ff06f_0390045b,
-    64'h03a0055b_10052423,
+    64'h03a0055b_10052223,
     64'h00100073_0390045b,
-    64'h03a0055b_10052c23,
+    64'h03a0055b_10052623,
     64'h00c51513_00c55513,
     64'h00000517_fd5ff06f,
     64'hfa041ce3_00247413,
@@ -51,15 +50,11 @@ module debug_rom (
     64'h07c0006f_00c0006f
   };
 
-  logic [$clog2(RomSize)-1:0] addr_d, addr_q;
+  logic [$clog2(RomSize)-1:0] addr_q;
 
-  assign addr_d = req_i ? addr_i[$clog2(RomSize)-1+3:3] : addr_q;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      addr_q <= '0;
-    end else begin
-      addr_q <= addr_d;
+  always_ff @(posedge clk_i) begin
+    if (req_i) begin
+      addr_q <= addr_i[$clog2(RomSize)-1+3:3];
     end
   end
 
@@ -68,7 +63,7 @@ module debug_rom (
   always_comb begin : p_outmux
     rdata_o = '0;
     if (addr_q < $clog2(RomSize)'(RomSize)) begin
-      rdata_o = mem[addr_q];
+        rdata_o = mem[addr_q];
     end
   end
 

hw/vendor/cheriot_debug_module/debug_rom/debug_rom_one_scratch.h

@@ -1,14 +1,11 @@
 // Auto-generated code
 
-const int reset_vec_size = 28;
+const int reset_vec_size = 26;
 
 uint32_t reset_vec[reset_vec_size] = {
-    0x0180006f,
-    0x00000013,
-    0x0580006f,
-    0x00000013,
-    0x0380006f,
-    0x00000013,
+    0x00c0006f,
+    0x0500006f,
+    0x0340006f,
     0x0ff0000f,
     0x7b241073,
     0xf1402473,
@@ -19,16 +16,17 @@ uint32_t reset_vec[reset_vec_size] = {
     0xf1402473,
     0x40044403,
     0x00247413,
-    0xfc0414e3,
+    0xfc0418e3,
     0xfddff06f,
-    0x10002c23,
+    0x10002623,
     0x7b202473,
     0x00100073,
-    0x10002423,
+    0x10002223,
     0x7b202473,
-    0xaa5ff06f,
+    0xab1ff06f,
     0xf1402473,
-    0x10802823,
+    0x10802423,
     0x7b202473,
-    0x7b200073
+    0x7b200073,
+    0x00000000
 };