@@ -282,6 +282,10 @@ typedef enum S390Opcode {
282
282
VRRc_VESRAV = 0xe77a ,
283
283
VRRc_VESRLV = 0xe778 ,
284
284
VRRc_VML = 0xe7a2 ,
285
+ VRRc_VMN = 0xe7fe ,
286
+ VRRc_VMNL = 0xe7fc ,
287
+ VRRc_VMX = 0xe7ff ,
288
+ VRRc_VMXL = 0xe7fd ,
285
289
VRRc_VN = 0xe768 ,
286
290
VRRc_VNC = 0xe769 ,
287
291
VRRc_VNO = 0xe76b ,
@@ -2767,6 +2771,19 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
2767
2771
tcg_out_insn (s, VRRc, VERLLV, a0, a1, a2, vece);
2768
2772
break ;
2769
2773
2774
+ case INDEX_op_smin_vec:
2775
+ tcg_out_insn (s, VRRc, VMN, a0, a1, a2, vece);
2776
+ break ;
2777
+ case INDEX_op_smax_vec:
2778
+ tcg_out_insn (s, VRRc, VMX, a0, a1, a2, vece);
2779
+ break ;
2780
+ case INDEX_op_umin_vec:
2781
+ tcg_out_insn (s, VRRc, VMNL, a0, a1, a2, vece);
2782
+ break ;
2783
+ case INDEX_op_umax_vec:
2784
+ tcg_out_insn (s, VRRc, VMXL, a0, a1, a2, vece);
2785
+ break ;
2786
+
2770
2787
case INDEX_op_cmp_vec:
2771
2788
switch ((TCGCond)args[3 ]) {
2772
2789
case TCG_COND_EQ:
@@ -2813,7 +2830,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
2813
2830
case INDEX_op_shri_vec:
2814
2831
case INDEX_op_shrs_vec:
2815
2832
case INDEX_op_shrv_vec:
2833
+ case INDEX_op_smax_vec:
2834
+ case INDEX_op_smin_vec:
2816
2835
case INDEX_op_sub_vec:
2836
+ case INDEX_op_umax_vec:
2837
+ case INDEX_op_umin_vec:
2817
2838
case INDEX_op_xor_vec:
2818
2839
return 1 ;
2819
2840
case INDEX_op_cmp_vec:
@@ -3074,6 +3095,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
3074
3095
case INDEX_op_shlv_vec:
3075
3096
case INDEX_op_shrv_vec:
3076
3097
case INDEX_op_sarv_vec:
3098
+ case INDEX_op_smax_vec:
3099
+ case INDEX_op_smin_vec:
3100
+ case INDEX_op_umax_vec:
3101
+ case INDEX_op_umin_vec:
3077
3102
return C_O1_I2 (v, v, v);
3078
3103
case INDEX_op_rotls_vec:
3079
3104
case INDEX_op_shls_vec:
0 commit comments