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LIU Zhiweialistair23
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target/riscv: vector compress instruction
Signed-off-by: LIU Zhiwei <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
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4 files changed

+64
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target/riscv/helper.h

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@@ -1145,3 +1145,8 @@ DEF_HELPER_6(vrgather_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vrgather_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vrgather_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vrgather_vx_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)

target/riscv/insn32.decode

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Original file line numberDiff line numberDiff line change
@@ -577,6 +577,7 @@ vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm
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vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm
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vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
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vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
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vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
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vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
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vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

target/riscv/insn_trans/trans_rvv.inc.c

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Original file line numberDiff line numberDiff line change
@@ -2854,3 +2854,35 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
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}
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return true;
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}
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/* Vector Compress Instruction */
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static bool vcompress_vm_check(DisasContext *s, arg_r *a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_reg(s, a->rd, false) &&
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vext_check_reg(s, a->rs2, false) &&
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vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) &&
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(a->rd != a->rs2));
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}
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static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
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{
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if (vcompress_vm_check(s, a)) {
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uint32_t data = 0;
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static gen_helper_gvec_4_ptr * const fns[4] = {
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gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h,
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gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d,
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};
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TCGLabel *over = gen_new_label();
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tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
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data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
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vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
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cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
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gen_set_label(over);
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return true;
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}
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return false;
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}

target/riscv/vector_helper.c

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Original file line numberDiff line numberDiff line change
@@ -4871,3 +4871,29 @@ GEN_VEXT_VRGATHER_VX(vrgather_vx_b, uint8_t, H1, clearb)
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GEN_VEXT_VRGATHER_VX(vrgather_vx_h, uint16_t, H2, clearh)
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GEN_VEXT_VRGATHER_VX(vrgather_vx_w, uint32_t, H4, clearl)
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GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq)
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/* Vector Compress Instruction */
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#define GEN_VEXT_VCOMPRESS_VM(NAME, ETYPE, H, CLEAR_FN) \
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void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
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CPURISCVState *env, uint32_t desc) \
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{ \
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uint32_t mlen = vext_mlen(desc); \
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uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
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uint32_t vl = env->vl; \
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uint32_t num = 0, i; \
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\
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for (i = 0; i < vl; i++) { \
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if (!vext_elem_mask(vs1, mlen, i)) { \
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continue; \
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} \
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*((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \
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num++; \
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} \
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CLEAR_FN(vd, num, num * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
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}
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/* Compress into vd elements of vs2 where vs1 is enabled */
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GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1, clearb)
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GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2, clearh)
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GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4, clearl)
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GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8, clearq)

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