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LIU Zhiweialistair23
LIU Zhiwei
authored and
alistair23
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target/riscv: vector register gather instruction
Signed-off-by: LIU Zhiwei <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
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4 files changed

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‎target/riscv/helper.h‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1136,3 +1136,12 @@ DEF_HELPER_6(vslide1down_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vslide1down_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vslide1down_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vslide1down_vx_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vrgather_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vrgather_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vrgather_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vrgather_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vrgather_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vrgather_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vrgather_vx_w, void, ptr, ptr, tl, ptr, env, i32)
1147+
DEF_HELPER_6(vrgather_vx_d, void, ptr, ptr, tl, ptr, env, i32)

‎target/riscv/insn32.decode‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -574,6 +574,9 @@ vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm
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vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm
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vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm
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vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm
577+
vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm
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vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
579+
vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
577580

578581
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
579582
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

‎target/riscv/insn_trans/trans_rvv.inc.c‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2776,3 +2776,81 @@ GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
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GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
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GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
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GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
2779+
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/* Vector Register Gather Instruction */
2781+
static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
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{
2783+
return (vext_check_isa_ill(s) &&
2784+
vext_check_overlap_mask(s, a->rd, a->vm, true) &&
2785+
vext_check_reg(s, a->rd, false) &&
2786+
vext_check_reg(s, a->rs1, false) &&
2787+
vext_check_reg(s, a->rs2, false) &&
2788+
(a->rd != a->rs2) && (a->rd != a->rs1));
2789+
}
2790+
2791+
GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check)
2792+
2793+
static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
2794+
{
2795+
return (vext_check_isa_ill(s) &&
2796+
vext_check_overlap_mask(s, a->rd, a->vm, true) &&
2797+
vext_check_reg(s, a->rd, false) &&
2798+
vext_check_reg(s, a->rs2, false) &&
2799+
(a->rd != a->rs2));
2800+
}
2801+
2802+
/* vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
2803+
static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
2804+
{
2805+
if (!vrgather_vx_check(s, a)) {
2806+
return false;
2807+
}
2808+
2809+
if (a->vm && s->vl_eq_vlmax) {
2810+
int vlmax = s->vlen / s->mlen;
2811+
TCGv_i64 dest = tcg_temp_new_i64();
2812+
2813+
if (a->rs1 == 0) {
2814+
vec_element_loadi(s, dest, a->rs2, 0);
2815+
} else {
2816+
vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
2817+
}
2818+
2819+
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
2820+
MAXSZ(s), MAXSZ(s), dest);
2821+
tcg_temp_free_i64(dest);
2822+
} else {
2823+
static gen_helper_opivx * const fns[4] = {
2824+
gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
2825+
gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
2826+
};
2827+
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);
2828+
}
2829+
return true;
2830+
}
2831+
2832+
/* vrgather.vi vd, vs2, imm, vm # vd[i] = (imm >= VLMAX) ? 0 : vs2[imm] */
2833+
static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
2834+
{
2835+
if (!vrgather_vx_check(s, a)) {
2836+
return false;
2837+
}
2838+
2839+
if (a->vm && s->vl_eq_vlmax) {
2840+
if (a->rs1 >= s->vlen / s->mlen) {
2841+
tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
2842+
MAXSZ(s), MAXSZ(s), 0);
2843+
} else {
2844+
tcg_gen_gvec_dup_mem(s->sew, vreg_ofs(s, a->rd),
2845+
endian_ofs(s, a->rs2, a->rs1),
2846+
MAXSZ(s), MAXSZ(s));
2847+
}
2848+
} else {
2849+
static gen_helper_opivx * const fns[4] = {
2850+
gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
2851+
gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
2852+
};
2853+
return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, 1);
2854+
}
2855+
return true;
2856+
}

‎target/riscv/vector_helper.c‎

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4811,3 +4811,63 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1, clearb)
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GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2, clearh)
48124812
GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4, clearl)
48134813
GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq)
4814+
4815+
/* Vector Register Gather Instruction */
4816+
#define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H, CLEAR_FN) \
4817+
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
4818+
CPURISCVState *env, uint32_t desc) \
4819+
{ \
4820+
uint32_t mlen = vext_mlen(desc); \
4821+
uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
4822+
uint32_t vm = vext_vm(desc); \
4823+
uint32_t vl = env->vl; \
4824+
uint32_t index, i; \
4825+
\
4826+
for (i = 0; i < vl; i++) { \
4827+
if (!vm && !vext_elem_mask(v0, mlen, i)) { \
4828+
continue; \
4829+
} \
4830+
index = *((ETYPE *)vs1 + H(i)); \
4831+
if (index >= vlmax) { \
4832+
*((ETYPE *)vd + H(i)) = 0; \
4833+
} else { \
4834+
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \
4835+
} \
4836+
} \
4837+
CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
4838+
}
4839+
4840+
/* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */
4841+
GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, H1, clearb)
4842+
GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, H2, clearh)
4843+
GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, H4, clearl)
4844+
GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8, clearq)
4845+
4846+
#define GEN_VEXT_VRGATHER_VX(NAME, ETYPE, H, CLEAR_FN) \
4847+
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
4848+
CPURISCVState *env, uint32_t desc) \
4849+
{ \
4850+
uint32_t mlen = vext_mlen(desc); \
4851+
uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
4852+
uint32_t vm = vext_vm(desc); \
4853+
uint32_t vl = env->vl; \
4854+
uint32_t index = s1, i; \
4855+
\
4856+
for (i = 0; i < vl; i++) { \
4857+
if (!vm && !vext_elem_mask(v0, mlen, i)) { \
4858+
continue; \
4859+
} \
4860+
if (index >= vlmax) { \
4861+
*((ETYPE *)vd + H(i)) = 0; \
4862+
} else { \
4863+
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \
4864+
} \
4865+
} \
4866+
CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
4867+
}
4868+
4869+
/* vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
4870+
GEN_VEXT_VRGATHER_VX(vrgather_vx_b, uint8_t, H1, clearb)
4871+
GEN_VEXT_VRGATHER_VX(vrgather_vx_h, uint16_t, H2, clearh)
4872+
GEN_VEXT_VRGATHER_VX(vrgather_vx_w, uint32_t, H4, clearl)
4873+
GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq)

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