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rth7680rth7680
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Merge remote-tracking branch 'remotes/rth/tags/pull-axp-20211013' into staging
Cleanup alpha memory ops prior to prctl PR_SET_UNALIGN # gpg: Signature made Wed 13 Oct 2021 10:34:10 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "[email protected]" # gpg: Good signature from "Richard Henderson <[email protected]>" [ultimate] * remotes/rth/tags/pull-axp-20211013: target/alpha: Reorg integer memory operations target/alpha: Reorg fp memory operations Signed-off-by: Richard Henderson <[email protected]>
2 parents 946de55 + 5ffcb33 commit 984b2b5

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‎target/alpha/translate.c‎

Lines changed: 90 additions & 83 deletions
Original file line numberDiff line numberDiff line change
@@ -267,51 +267,51 @@ static inline DisasJumpType gen_invalid(DisasContext *ctx)
267267
return gen_excp(ctx, EXCP_OPCDEC, 0);
268268
}
269269

270-
static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags)
270+
static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr)
271271
{
272272
TCGv_i32 tmp32 = tcg_temp_new_i32();
273-
tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL);
274-
gen_helper_memory_to_f(t0, tmp32);
273+
tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
274+
gen_helper_memory_to_f(dest, tmp32);
275275
tcg_temp_free_i32(tmp32);
276276
}
277277

278-
static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags)
278+
static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr)
279279
{
280280
TCGv tmp = tcg_temp_new();
281-
tcg_gen_qemu_ld_i64(tmp, t1, flags, MO_LEQ);
282-
gen_helper_memory_to_g(t0, tmp);
281+
tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
282+
gen_helper_memory_to_g(dest, tmp);
283283
tcg_temp_free(tmp);
284284
}
285285

286-
static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags)
286+
static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr)
287287
{
288288
TCGv_i32 tmp32 = tcg_temp_new_i32();
289-
tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL);
290-
gen_helper_memory_to_s(t0, tmp32);
289+
tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
290+
gen_helper_memory_to_s(dest, tmp32);
291291
tcg_temp_free_i32(tmp32);
292292
}
293293

294-
static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)
294+
static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr)
295295
{
296-
tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL);
297-
tcg_gen_mov_i64(cpu_lock_addr, t1);
298-
tcg_gen_mov_i64(cpu_lock_value, t0);
296+
tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ);
299297
}
300298

301-
static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags)
299+
static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
300+
void (*func)(DisasContext *, TCGv, TCGv))
302301
{
303-
tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LEQ);
304-
tcg_gen_mov_i64(cpu_lock_addr, t1);
305-
tcg_gen_mov_i64(cpu_lock_value, t0);
302+
/* Loads to $f31 are prefetches, which we can treat as nops. */
303+
if (likely(ra != 31)) {
304+
TCGv addr = tcg_temp_new();
305+
tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
306+
func(ctx, cpu_fir[ra], addr);
307+
tcg_temp_free(addr);
308+
}
306309
}
307310

308-
static inline void gen_load_mem(DisasContext *ctx,
309-
void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1,
310-
int flags),
311-
int ra, int rb, int32_t disp16, bool fp,
312-
bool clear)
311+
static void gen_load_int(DisasContext *ctx, int ra, int rb, int32_t disp16,
312+
MemOp op, bool clear, bool locked)
313313
{
314-
TCGv tmp, addr, va;
314+
TCGv addr, dest;
315315

316316
/* LDQ_U with ra $31 is UNOP. Other various loads are forms of
317317
prefetches, which we can treat as nops. No worries about
@@ -320,72 +320,75 @@ static inline void gen_load_mem(DisasContext *ctx,
320320
return;
321321
}
322322

323-
tmp = tcg_temp_new();
324-
addr = load_gpr(ctx, rb);
325-
326-
if (disp16) {
327-
tcg_gen_addi_i64(tmp, addr, disp16);
328-
addr = tmp;
329-
}
323+
addr = tcg_temp_new();
324+
tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
330325
if (clear) {
331-
tcg_gen_andi_i64(tmp, addr, ~0x7);
332-
addr = tmp;
326+
tcg_gen_andi_i64(addr, addr, ~0x7);
333327
}
334328

335-
va = (fp ? cpu_fir[ra] : ctx->ir[ra]);
336-
tcg_gen_qemu_load(va, addr, ctx->mem_idx);
329+
dest = ctx->ir[ra];
330+
tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, op);
337331

338-
tcg_temp_free(tmp);
332+
if (locked) {
333+
tcg_gen_mov_i64(cpu_lock_addr, addr);
334+
tcg_gen_mov_i64(cpu_lock_value, dest);
335+
}
336+
tcg_temp_free(addr);
339337
}
340338

341-
static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags)
339+
static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr)
342340
{
343341
TCGv_i32 tmp32 = tcg_temp_new_i32();
344-
gen_helper_f_to_memory(tmp32, t0);
345-
tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL);
342+
gen_helper_f_to_memory(tmp32, addr);
343+
tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
346344
tcg_temp_free_i32(tmp32);
347345
}
348346

349-
static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags)
347+
static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr)
350348
{
351349
TCGv tmp = tcg_temp_new();
352-
gen_helper_g_to_memory(tmp, t0);
353-
tcg_gen_qemu_st_i64(tmp, t1, flags, MO_LEQ);
350+
gen_helper_g_to_memory(tmp, src);
351+
tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
354352
tcg_temp_free(tmp);
355353
}
356354

357-
static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags)
355+
static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr)
358356
{
359357
TCGv_i32 tmp32 = tcg_temp_new_i32();
360-
gen_helper_s_to_memory(tmp32, t0);
361-
tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL);
358+
gen_helper_s_to_memory(tmp32, src);
359+
tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
362360
tcg_temp_free_i32(tmp32);
363361
}
364362

365-
static inline void gen_store_mem(DisasContext *ctx,
366-
void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1,
367-
int flags),
368-
int ra, int rb, int32_t disp16, bool fp,
369-
bool clear)
363+
static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr)
370364
{
371-
TCGv tmp, addr, va;
365+
tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ);
366+
}
372367

373-
tmp = tcg_temp_new();
374-
addr = load_gpr(ctx, rb);
368+
static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
369+
void (*func)(DisasContext *, TCGv, TCGv))
370+
{
371+
TCGv addr = tcg_temp_new();
372+
tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
373+
func(ctx, load_fpr(ctx, ra), addr);
374+
tcg_temp_free(addr);
375+
}
375376

376-
if (disp16) {
377-
tcg_gen_addi_i64(tmp, addr, disp16);
378-
addr = tmp;
379-
}
377+
static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp16,
378+
MemOp op, bool clear)
379+
{
380+
TCGv addr, src;
381+
382+
addr = tcg_temp_new();
383+
tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
380384
if (clear) {
381-
tcg_gen_andi_i64(tmp, addr, ~0x7);
382-
addr = tmp;
385+
tcg_gen_andi_i64(addr, addr, ~0x7);
383386
}
384387

385-
va = (fp ? load_fpr(ctx, ra) : load_gpr(ctx, ra));
386-
tcg_gen_qemu_store(va, addr, ctx->mem_idx);
388+
src = load_gpr(ctx, ra);
389+
tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, op);
387390

388-
tcg_temp_free(tmp);
391+
tcg_temp_free(addr);
389392
}
390393

391394
static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb,
@@ -1480,30 +1483,30 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
14801483
case 0x0A:
14811484
/* LDBU */
14821485
REQUIRE_AMASK(BWX);
1483-
gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0);
1486+
gen_load_int(ctx, ra, rb, disp16, MO_UB, 0, 0);
14841487
break;
14851488
case 0x0B:
14861489
/* LDQ_U */
1487-
gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1);
1490+
gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 1, 0);
14881491
break;
14891492
case 0x0C:
14901493
/* LDWU */
14911494
REQUIRE_AMASK(BWX);
1492-
gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0);
1495+
gen_load_int(ctx, ra, rb, disp16, MO_LEUW, 0, 0);
14931496
break;
14941497
case 0x0D:
14951498
/* STW */
14961499
REQUIRE_AMASK(BWX);
1497-
gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0);
1500+
gen_store_int(ctx, ra, rb, disp16, MO_LEUW, 0);
14981501
break;
14991502
case 0x0E:
15001503
/* STB */
15011504
REQUIRE_AMASK(BWX);
1502-
gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0);
1505+
gen_store_int(ctx, ra, rb, disp16, MO_UB, 0);
15031506
break;
15041507
case 0x0F:
15051508
/* STQ_U */
1506-
gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1);
1509+
gen_store_int(ctx, ra, rb, disp16, MO_LEQ, 1);
15071510
break;
15081511

15091512
case 0x10:
@@ -2458,11 +2461,15 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
24582461
break;
24592462
case 0x2:
24602463
/* Longword physical access with lock (hw_ldl_l/p) */
2461-
gen_qemu_ldl_l(va, addr, MMU_PHYS_IDX);
2464+
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL);
2465+
tcg_gen_mov_i64(cpu_lock_addr, addr);
2466+
tcg_gen_mov_i64(cpu_lock_value, va);
24622467
break;
24632468
case 0x3:
24642469
/* Quadword physical access with lock (hw_ldq_l/p) */
2465-
gen_qemu_ldq_l(va, addr, MMU_PHYS_IDX);
2470+
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEQ);
2471+
tcg_gen_mov_i64(cpu_lock_addr, addr);
2472+
tcg_gen_mov_i64(cpu_lock_value, va);
24662473
break;
24672474
case 0x4:
24682475
/* Longword virtual PTE fetch (hw_ldl/v) */
@@ -2776,66 +2783,66 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
27762783
case 0x20:
27772784
/* LDF */
27782785
REQUIRE_FEN;
2779-
gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0);
2786+
gen_load_fp(ctx, ra, rb, disp16, gen_ldf);
27802787
break;
27812788
case 0x21:
27822789
/* LDG */
27832790
REQUIRE_FEN;
2784-
gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0);
2791+
gen_load_fp(ctx, ra, rb, disp16, gen_ldg);
27852792
break;
27862793
case 0x22:
27872794
/* LDS */
27882795
REQUIRE_FEN;
2789-
gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0);
2796+
gen_load_fp(ctx, ra, rb, disp16, gen_lds);
27902797
break;
27912798
case 0x23:
27922799
/* LDT */
27932800
REQUIRE_FEN;
2794-
gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0);
2801+
gen_load_fp(ctx, ra, rb, disp16, gen_ldt);
27952802
break;
27962803
case 0x24:
27972804
/* STF */
27982805
REQUIRE_FEN;
2799-
gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0);
2806+
gen_store_fp(ctx, ra, rb, disp16, gen_stf);
28002807
break;
28012808
case 0x25:
28022809
/* STG */
28032810
REQUIRE_FEN;
2804-
gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0);
2811+
gen_store_fp(ctx, ra, rb, disp16, gen_stg);
28052812
break;
28062813
case 0x26:
28072814
/* STS */
28082815
REQUIRE_FEN;
2809-
gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0);
2816+
gen_store_fp(ctx, ra, rb, disp16, gen_sts);
28102817
break;
28112818
case 0x27:
28122819
/* STT */
28132820
REQUIRE_FEN;
2814-
gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0);
2821+
gen_store_fp(ctx, ra, rb, disp16, gen_stt);
28152822
break;
28162823
case 0x28:
28172824
/* LDL */
2818-
gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0);
2825+
gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 0);
28192826
break;
28202827
case 0x29:
28212828
/* LDQ */
2822-
gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0);
2829+
gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 0, 0);
28232830
break;
28242831
case 0x2A:
28252832
/* LDL_L */
2826-
gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0);
2833+
gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 1);
28272834
break;
28282835
case 0x2B:
28292836
/* LDQ_L */
2830-
gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0);
2837+
gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 0, 1);
28312838
break;
28322839
case 0x2C:
28332840
/* STL */
2834-
gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0);
2841+
gen_store_int(ctx, ra, rb, disp16, MO_LEUL, 0);
28352842
break;
28362843
case 0x2D:
28372844
/* STQ */
2838-
gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0);
2845+
gen_store_int(ctx, ra, rb, disp16, MO_LEQ, 0);
28392846
break;
28402847
case 0x2E:
28412848
/* STL_C */

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