Fix RV64M arithmetic semantics

[mateocabanal]

Motivation

• Correct several RV64M instruction implementations that produced incorrect results versus the RISC-V spec.
• Ensure W-sized (32-bit) variants and high-half multiply/divide/remainder instructions use the proper operand widths and edge-case behaviors.
• Fix load zero-extension semantics for LWU and remainder/divide-by-zero return values to match the architecture definition.

Description

• Change LWU to zero-extend the 32-bit loaded word into the 64-bit register by assigning u64::from(mem).
• Rework MUL, MULH, MULHSU, and MULHU to perform full-width multiplications and extract the correct 64-bit high/low halves using 128-bit intermediate arithmetic.
• Update REM/REMU to return the dividend when the divisor is zero, and keep the existing signed DIV/unsigned DIV behavior for divide-by-zero.
• Adjust 32-bit variants: MULW now multiplies 32-bit signed operands, DIVW adds the i32::MIN / -1 overflow check, and REMW/REMUW return the sign- or zero-extended dividend when the divisor is zero.

Testing

• No automated tests were executed as part of this change.
• The change was compiled/committed locally but no CI or unit test suite was run.
• Recommend running the repo's test matrix (e.g. cargo test and the tests/rv64* cases) in CI to validate instruction-level behavior.

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Codex Task