mathieuchopstm · mathieuchopstm · Nov 6, 2025 · Nov 6, 2025
diff --git a/TODO b/TODO
@@ -0,0 +1 @@
+* update code in HAL side
diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c
@@ -43,6 +43,8 @@
 #define ADC_CONTEXT_ENABLE_ON_COMPLETE
 #include "adc_context.h"
 
+#include <stm32_global_periph_clocks.h>
+
 #define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(adc_stm32);
@@ -1587,21 +1589,33 @@ static int adc_stm32_set_clock(const struct device *dev)
 
 static void adc_stm32_enable_analog_supply(void)
 {
+	if (IS_ENABLED(CONFIG_SOC_SERIES_STM32N6X) ||
+	    IS_ENABLED(CONFIG_SOC_SERIES_STM32U5X) ||
+	    IS_ENABLED(CONFIG_SOC_SERIES_STM32U3X)) {
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 #if defined(CONFIG_SOC_SERIES_STM32N6X)
-	LL_PWR_EnableVddADC();
+		LL_PWR_EnableVddADC();
 #elif defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32U3X)
-	LL_PWR_EnableVDDA();
+		LL_PWR_EnableVDDA();
 #endif /* CONFIG_SOC_SERIES_STM32U5X */
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+	}
 }
 
 #ifdef CONFIG_PM_DEVICE
 static void adc_stm32_disable_analog_supply(void)
 {
+	if (IS_ENABLED(CONFIG_SOC_SERIES_STM32N6X) ||
+	    IS_ENABLED(CONFIG_SOC_SERIES_STM32U5X) ||
+	    IS_ENABLED(CONFIG_SOC_SERIES_STM32U3X)) {
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 #if defined(CONFIG_SOC_SERIES_STM32N6X)
 	LL_PWR_DisableVddADC();
 #elif defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32U3X)
 	LL_PWR_DisableVDDA();
 #endif /* CONFIG_SOC_SERIES_STM32U5X */
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+	}
 }
 #endif
 

diff --git a/drivers/adc/adc_stm32wb0.c b/drivers/adc/adc_stm32wb0.c
@@ -47,6 +47,7 @@
 
 #include <soc.h>
 #include <stm32_bitops.h>
+#include <stm32_global_periph_clocks.h>
 #include <stm32_ll_adc.h>
 #include <stm32_ll_utils.h>
 
@@ -1101,8 +1102,10 @@ int adc_stm32wb0_init(const struct device *dev)
 #endif
 
 #if defined(PWR_CR2_ENTS)
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 	/* Enable on-die temperature sensor */
 	LL_PWR_EnableTempSens();
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 #endif
 
 	/* Set ADC sample rate to 1 Msps (maximum speed) */

diff --git a/drivers/bluetooth/hci/hci_stm32wb0.c b/drivers/bluetooth/hci/hci_stm32wb0.c
@@ -320,12 +320,16 @@ static int ble_pm_action(const struct device *dev,
 
 	switch (action) {
 	case PM_DEVICE_ACTION_SUSPEND:
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 		LL_PWR_EnableWU_EWBLE();
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 		pka_cr_vr = PKA->CR;
 		/* TBD: Manage PKA save for WB06 & WB07 */
 		break;
 	case PM_DEVICE_ACTION_RESUME:
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 		LL_PWR_DisableWU_EWBLE();
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 		/* TBD: Manage PKA restore for WB06 & WB07 */
 		PKA->CLRFR = PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC;
 		PKA->CR = pka_cr_vr;

diff --git a/drivers/bluetooth/hci/hci_stm32wba.c b/drivers/bluetooth/hci/hci_stm32wba.c
@@ -21,6 +21,8 @@
 #endif /* CONFIG_PM_DEVICE */
 #include <linklayer_plat_local.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <zephyr/sys/byteorder.h>
 
 #include "blestack.h"
@@ -561,10 +563,12 @@ static int radio_pm_action(const struct device *dev, enum pm_device_action actio
 	case PM_DEVICE_ACTION_RESUME:
 		LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_RADIO);
 #if defined(CONFIG_PM_S2RAM)
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 		if (LL_PWR_IsActiveFlag_SB() == 1U) {
 			/* Put the radio in active state */
 			link_layer_register_isr();
 		}
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 #endif /* CONFIG_PM_S2RAM */
 		LINKLAYER_PLAT_NotifyWFIExit();
 		ll_sys_dp_slp_exit();

diff --git a/drivers/bluetooth/hci/ipm_stm32wb.c b/drivers/bluetooth/hci/ipm_stm32wb.c
@@ -16,6 +16,8 @@
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/irq.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include "app_conf.h"
 #include "stm32_wpan_common.h"
 #include "shci.h"
@@ -545,8 +547,10 @@
 	if (!c2_started_flag) {
 		/* C2 has been teared down. Reinit required */
 		SHCI_C2_Reinit();
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR); //TODO: before C2_Reinit?
 		while (LL_PWR_IsActiveFlag_C2DS() == 0) {
 		};
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 
 		err = c2_reset();
 		if (err) {
@@ -599,8 +603,10 @@
 	}
 
 	/* Wait till C2DS set */
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 	while (LL_PWR_IsActiveFlag_C2DS() == 0) {
 	};
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 
 	c2_started_flag = false;
 

diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c
@@ -17,6 +17,7 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/__assert.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <stm32_global_periph_clocks.h>
 #include <stm32_backup_domain.h>
 #include <stm32_hsem.h>
 
@@ -1027,8 +1028,9 @@ static void set_up_fixed_clock_sources(void)
 		 * HSI48 requires VREFINT (see RM0376 section 7.2.4).
 		 * The SYSCFG is needed to control VREFINT, so clock it.
 		 */
-		LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_SYSCFG);
 		LL_SYSCFG_VREFINT_EnableHSI48();
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
 #endif /* CONFIG_SOC_SERIES_STM32L0X */
 
 		/*

diff --git a/drivers/clock_control/clock_stm32_ll_h5.c b/drivers/clock_control/clock_stm32_ll_h5.c
@@ -19,6 +19,7 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <stm32_backup_domain.h>
+#include <stm32_global_periph_clocks.h>
 
 /* Macros to fill up prescaler values */
 #define z_hsi_divider(v) LL_RCC_HSI_DIV_ ## v
@@ -438,6 +439,8 @@ static uint32_t get_vco_output_range(uint32_t vco_input_range)
 
 static void set_regu_voltage(uint32_t hclk_freq)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	if (hclk_freq <= MHZ(100)) {
 		LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE3);
 	} else if (hclk_freq <= MHZ(150)) {
@@ -449,6 +452,8 @@ static void set_regu_voltage(uint32_t hclk_freq)
 	}
 	while (LL_PWR_IsActiveFlag_VOS() == 0) {
 	}
+
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 }
 
 __unused

diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c
@@ -16,6 +16,7 @@
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <stm32_global_periph_clocks.h>
 #include <stm32_backup_domain.h>
 #include <stm32_hsem.h>
 
@@ -1025,6 +1026,9 @@ int stm32_clock_control_init(const struct device *dev)
 {
 	int r = 0;
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
+
 #if defined(CONFIG_CPU_CORTEX_M7)
 	uint32_t old_hclk_freq;
 	uint32_t new_hclk_freq;
@@ -1142,6 +1146,8 @@ int stm32_clock_control_init(const struct device *dev)
 		LL_RCC_SetTIMPrescaler(LL_RCC_TIM_PRESCALER_TWICE);
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	ARG_UNUSED(dev);
 
 	/* Update CMSIS variable */

diff --git a/drivers/clock_control/clock_stm32_ll_n6.c b/drivers/clock_control/clock_stm32_ll_n6.c
@@ -892,9 +892,6 @@ static void set_up_fixed_clock_sources(void)
 	}
 
 	if (IS_ENABLED(STM32_LSE_ENABLED)) {
-		/* Enable the power interface clock */
-		LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
-
 		stm32_backup_domain_enable_access();
 
 		/* Configure driving capability */

diff --git a/drivers/clock_control/clock_stm32_ll_u3.c b/drivers/clock_control/clock_stm32_ll_u3.c
@@ -15,6 +15,7 @@
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/sys/util.h>
 #include <stm32_backup_domain.h>
+#include <stm32_global_periph_clocks.h>
 
 /* Macros to fill up prescaler values */
 #define ahb_prescaler(v) CONCAT(LL_RCC_HCLK_SYSCLK_DIV_, v)
@@ -575,6 +576,8 @@ int stm32_clock_control_init(const struct device *dev)
 
 	ARG_UNUSED(dev);
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	/* Current hclk value */
 	old_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(get_startup_frequency(), LL_RCC_GetAHBPrescaler());
 
@@ -621,6 +624,8 @@ int stm32_clock_control_init(const struct device *dev)
 		LL_SetFlashLatency(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/* Update CMSIS variable */
 	SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
 

diff --git a/drivers/clock_control/clock_stm32_ll_u5.c b/drivers/clock_control/clock_stm32_ll_u5.c
@@ -19,6 +19,7 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <stm32_backup_domain.h>
+#include <stm32_global_periph_clocks.h>
 
 /* Macros to fill up prescaler values */
 #define z_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
@@ -744,9 +745,6 @@ static void set_up_fixed_clock_sources(void)
 	}
 
 	if (IS_ENABLED(STM32_LSE_ENABLED)) {
-		/* Enable the power interface clock */
-		LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
-
 		stm32_backup_domain_enable_access();
 
 		/* Configure driving capability */
@@ -822,11 +820,6 @@ static void set_up_fixed_clock_sources(void)
 	}
 
 	if (IS_ENABLED(STM32_LSI_ENABLED)) {
-		if (!LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PWR)) {
-			/* Enable the power interface clock */
-			LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
-		}
-
 		stm32_backup_domain_enable_access();
 
 		/* Enable LSI oscillator */
@@ -851,6 +844,9 @@ int stm32_clock_control_init(const struct device *dev)
 
 	ARG_UNUSED(dev);
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
+
 	/* Current hclk value */
 	old_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(get_startup_frequency(), LL_RCC_GetAHBPrescaler());
 
@@ -922,6 +918,8 @@ int stm32_clock_control_init(const struct device *dev)
 		LL_SetFlashLatency(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/* Update CMSIS variable */
 	SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
 

diff --git a/drivers/clock_control/clock_stm32_ll_wb0.c b/drivers/clock_control/clock_stm32_ll_wb0.c
@@ -21,6 +21,8 @@
 #include <zephyr/arch/common/sys_bitops.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 
+#include <stm32_global_periph_clocks.h>
+
 /* Driver definitions */
 #define RCC_REG(_reg_offset) (DT_REG_ADDR(STM32_CLOCK_CONTROL_NODE) + (_reg_offset))
 #define RADIO_CTRL_IRQn		21	/* Not provided by CMSIS; must be declared manually */
@@ -570,8 +572,11 @@ static void set_up_fixed_clock_sources(void)
 		/* Configure driving capability */
 		LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_CSSWCR_LSEDRV_Pos);
 #endif
+
 		/* Unconditionally disable pull-up & pull-down on LSE pins */
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 		LL_PWR_SetNoPullB(LL_PWR_GPIO_BIT_12 | LL_PWR_GPIO_BIT_13);
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 
 		if (IS_ENABLED(STM32_LSE_BYPASS)) {
 			/* Configure LSE bypass */
@@ -716,9 +721,6 @@ int stm32_clock_control_init(const struct device *dev)
 			: LL_FLASH_LATENCY_0
 	);
 
-	/* Unconditionally enable SYSCFG clock for other drivers */
-	LL_APB0_GRP1_EnableClock(LL_APB0_GRP1_PERIPH_SYSCFG);
-
 	/* Set up indiviual enabled clocks */
 	set_up_fixed_clock_sources();
 

diff --git a/drivers/clock_control/clock_stm32_ll_wba.c b/drivers/clock_control/clock_stm32_ll_wba.c
@@ -14,6 +14,7 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/__assert.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <stm32_global_periph_clocks.h>
 #include <stm32_backup_domain.h>
 #include <stm32_hsem.h>
 
@@ -345,13 +346,15 @@ static int get_vco_input_range(uint32_t m_div, uint32_t *range)
 
 static void set_regu_voltage(uint32_t hclk_freq)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 	if (hclk_freq <= MHZ(16)) {
 		LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
 	} else {
 		LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
 	}
 	while (LL_PWR_IsActiveFlag_VOS() == 0) {
 	}
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 }
 
 /*

diff --git a/drivers/clock_control/clock_stm32c0.c b/drivers/clock_control/clock_stm32c0.c
@@ -21,9 +21,6 @@
  */
 void config_enable_default_clocks(void)
 {
-	/* Enable the power interface clock */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-
 #if IS_ENABLED(STM32_HSI48_CRS_USB_SOF)
 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS);
 	LL_CRS_SetSyncSignalSource(LL_CRS_SYNC_SOURCE_USB);

diff --git a/drivers/clock_control/clock_stm32f0_f3.c b/drivers/clock_control/clock_stm32f0_f3.c
@@ -144,20 +144,4 @@ uint32_t get_pllout_frequency(void)
  */
 void config_enable_default_clocks(void)
 {
-	/* Enable PWR clock, required to access BDCR and PWR_CR */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-
-#ifndef CONFIG_SOC_SERIES_STM32F3X
-#if defined(CONFIG_EXTI_STM32) || defined(CONFIG_USB_DC_STM32)
-	/* Enable System Configuration Controller clock. */
-	LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
-#endif
-#else
-#if defined(CONFIG_USB_DC_STM32) && defined(SYSCFG_CFGR1_USB_IT_RMP)
-	/* Enable System Configuration Controller clock. */
-	/* SYSCFG is required to remap IRQ to avoid conflicts with CAN */
-	/* cf §14.1.3, RM0316 */
-	LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
-#endif
-#endif /* !CONFIG_SOC_SERIES_STM32F3X */
 }
diff --git a/drivers/clock_control/clock_stm32f1.c b/drivers/clock_control/clock_stm32f1.c
@@ -169,7 +169,6 @@ void config_enable_default_clocks(void)
 {
 	if (IS_ENABLED(STM32_LSE_ENABLED)) {
 		/* Set the PWREN and BKPEN bits in the RCC_APB1ENR register */
-		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_BKP);
 	}
 }
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		* update code in HAL side
Check warning on line 1 in TODO View workflow job for this annotation GitHub Actions / Run compliance checks on patch series (PR) Copyright missing `TODO:1 File has no SPDX-FileCopyrightText header, consider adding one.` Check warning on line 1 in TODO View workflow job for this annotation GitHub Actions / Run compliance checks on patch series (PR) License missing `TODO:1 File has no SPDX-License-Identifier header, consider adding one.`