Upstream sg13g2 changes (#47)

* reduced cache ports to 1RW

* porting

* async reset

* update

* update

* back to default config

* explicity set non-reset regs to undefined

* back to sync reset

* remove sg13g2 specific code

* comment for easily switching between sync/async reset

* update model headers

* Split CacheLineManager from LSU

* no competitive CT reads

* basic prefetch infrastructure

* prefetch improvements

* prefetch fixes

* reduce shift register size

* per-cacheline replacement idx counter

Author: mathis-s

Makefile

@@ -65,8 +65,6 @@ SRC_FILES = \
 	src/IFetchPipeline.sv \
 	src/CSR.sv \
 	src/TrapHandler.sv \
-	src/CacheInterface.sv \
-	src/MemoryInterface.sv \
 	src/Peripherals.sv \
 	src/PageWalker.sv \
 	src/LoadSelector.sv \
@@ -92,6 +90,15 @@ SRC_FILES = \
 	src/ResultFlagsSplit.sv \
 	src/InstrAligner.sv \
 	src/RFReadMux.sv \
+	src/CacheArbiter.sv \
+	src/MemRTL1RW.sv \
+	src/ExternalBus.sv \
+	src/ExternalBusMem.sv \
+	src/CacheLineManager.sv \
+	src/DataPrefetch.sv \
+	src/PrefetchPatternDetector.sv \
+	src/PrefetchIssuer.sv \
+	src/PrefetchExecutor.sv \
 	hardfloat/addRecFN.v \
 	hardfloat/compareRecFN.v \
 	hardfloat/fNToRecFN.v \

sim/Inst.hpp

@@ -14,8 +14,8 @@ struct Inst
     uint32_t memAddr;
     uint32_t memData;
     uint32_t predTarget;
-    uint8_t fetchID;
-    uint8_t sqn;
+    uint16_t fetchID;
+    uint16_t sqn;
     uint8_t fu;
     uint8_t rd;
     uint16_t tag;

sim/model_headers.h

@@ -6,7 +6,6 @@
 #include "VTop_RegFile__W50_S20_N1_NB1.h"
 #include "VTop_ExternalAXISim.h"
 #include "VTop_RenameTable__ND5.h"
-#include "VTop_MemRTL__W54_N40_WB15.h"
 #include "VTop_ROB.h"
 #include "VTop_Top.h"
 #include "VTop_IFetchPipeline.h"
@@ -17,6 +16,7 @@
 #include "VTop_IF_Cache.h"
 #include "VTop__Dpi.h"
 #include "VTop_IF_MMIO.h"
+#include "VTop_MemRTL1RW__W54_N40_WB15.h"
 #include "VTop_BranchPredictor__N3.h"
 #include "VTop_RegFile__NB5_A1.h"
 #include "VTop_ReturnStack.h"

sim/models/BranchHistory.hpp

@@ -22,7 +22,7 @@ class BranchHistory : public Model
         auto core = top->Top->soc->core;
         auto bpFile = core->ifetch->bp->bpFile->mem;
 
-        BPBackup backup{sc_bv<BPBackup::_size>{(char*)bpFile[fetchID].data()}};
+        BPBackup backup{sc_bv<BPBackup::_size>{(char*)&bpFile[fetchID]}};
 
         if (backup.pred && backup.isRegularBranch && fetchOffs > backup.predOffs)
             return (backup.history << 1) | backup.predTaken;
@@ -34,9 +34,12 @@ class BranchHistory : public Model
 
     bool compare_history (const Inst& i)
     {
-        auto fetchOffset = (((i.pc & 15) >> 1) + (((i.inst & 3) == 3) ? 1 : 0)) & 7;
+        constexpr uint64_t bhist_mask = BPBackup::history_w == 64 ? (-1) : ((1UL << BPBackup::history_w) - 1);
+        constexpr uint64_t fetchoffs_mask = (1UL << BPBackup::predOffs_w) - 1;
+
+        auto fetchOffset = (((i.pc) >> 1) + (((i.inst & 3) == 3) ? 1 : 0)) & fetchoffs_mask;
         auto coreHist = ReadBrHistory(i.fetchID, fetchOffset);
-        return coreHist == bhist;
+        return (coreHist & bhist_mask) == (bhist & bhist_mask);
     }
 
     std::pair<bool, bool> is_branch_taken (uint32_t instSIM)