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Fix & Feat: Improve Verilator 5.040 compatibility and fix FP compilation issues #56

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Fix & Feat: Improve Verilator 5.040 compatibility and fix FP compilation issues #56

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3c51d9c
Feat: Added explanations of the sources of header files in model_head…
CelestialMelody Jan 7, 2026
e05d6a7
Fix: Solve the Warning-PROCASSINIT issue in Verilator 5.040. A variab…
CelestialMelody Jan 7, 2026
dd82205
Feat: Solve the issue of different Verilator versions supporting -Wno…
CelestialMelody Jan 7, 2026
ec9a7c7
Fix: If `define ENABLE_FP is set in Config.sv, a compilation error wi…
CelestialMelody Jan 7, 2026
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16 changes: 11 additions & 5 deletions Makefile
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Original file line number Diff line number Diff line change
@@ -1,9 +1,15 @@
ifeq ($(shell verilator -Wno-GENUNNAMED --version >/dev/null 2>&1 && echo YES),YES)
SUPPORTS_GENUNNAMED := -Wno-GENUNNAMED
endif

VERILATOR_FLAGS = \
--cc --build --threads 4 --unroll-stmts 999999 -unroll-count 999999 --assert -Wall -Wno-BLKSEQ -Wno-UNUSED \
-Wno-PINCONNECTEMPTY -Wno-DECLFILENAME -Wno-ENUMVALUE -Wno-GENUNNAMED -O3 -sv \
$(VFLAGS) \
-CFLAGS "-std=c++17 -march=native" \
-LDFLAGS "-ldl" \
--cc --build --threads 4 --unroll-stmts 999999 -unroll-count 999999 --assert -Wall \
-Wno-BLKSEQ -Wno-UNUSED -Wno-PINCONNECTEMPTY -Wno-DECLFILENAME -Wno-ENUMVALUE \
$(SUPPORTS_GENUNNAMED) \
-O3 -sv \
$(VFLAGS) \
-CFLAGS "-std=c++17 -march=native" \
-LDFLAGS "-ldl" \
-MAKEFLAGS -j$(nproc) \
-CFLAGS -DNOKONATA \
-CFLAGS -DCOSIM \
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64 changes: 42 additions & 22 deletions sim/model_headers.h
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@mathis-s mathis-s Jan 24, 2026 •
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This file is autogenerated, there shouldn't be any comments in here, these will be overwritten when regenerating. I'd prefer as few changes here as possible

Original file line number Diff line number Diff line change
@@ -1,31 +1,51 @@
#include "VTop_TagBuffer.h"
#include "VTop_CSR.h"
#include "VTop_Rename__WC5.h"
#include "VTop_IF_ICTable.h"
// Include all *.h files in obj_dir (auto-generated by Verilator)
// Use `make prepare_header` to regenerate
// Top-level core header file
#include "VTop.h"
#include "VTop_RegFile__W50_S20_N1_NB1.h"
#include "VTop_ExternalAXISim.h"
#include "VTop_RenameTable__ND5.h"
#include "VTop_ROB.h"
#include "VTop_Top.h"
#include "VTop_IFetchPipeline.h"
#include "VTop_MemRTL__W200_N40.h"
#include "VTop_StoreQueue.h"

// Root module and global unit header files
#include "VTop___024root.h"
#include "VTop___024unit.h"

// Core module related
#include "VTop_Core.h"
#include "VTop_CSR.h"

// Branch prediction related
#include "VTop_BranchPredictor__N3.h"
#include "VTop_ReturnStack.h"

// SoC and external modules
#include "VTop_SoC.h"
#include "VTop_ExternalAXISim.h"

// Instruction fetch stage related
#include "VTop_IFetch.h"
#include "VTop_IFetchPipeline.h"
#include "VTop_IF_Cache.h"
#include "VTop__Dpi.h"
#include "VTop_IF_CTable.h"
#include "VTop_IF_ICache.h"
#include "VTop_IF_ICTable.h"
#include "VTop_IF_MMIO.h"

// Memory module related
#include "VTop_MemRTL__W200_N40.h"
#include "VTop_MemRTL__W200_N100_WB80.h"
#include "VTop_MemRTL1RW__W2_N40_WB2.h"
#include "VTop_MemRTL1RW__W54_N40_WB15.h"
#include "VTop_BranchPredictor__N3.h"
#include "VTop_StoreQueue.h"
#include "VTop_ROB.h"

// Register file and rename related
#include "VTop_RegFile__NB5_A1.h"
#include "VTop_ReturnStack.h"
#include "VTop_Core.h"
#include "VTop_IF_ICache.h"
#include "VTop_RegFile__W23_S20_N3_NB1.h"
#include "VTop_SoC.h"
#include "VTop___024unit.h"
#include "VTop_MemRTL__W200_N100_WB80.h"
#include "VTop__Syms.h"
#include "VTop__pch.h"
#include "VTop_IF_CTable.h"
#include "VTop_RegFile__W50_S20_N1_NB1.h"
#include "VTop_RenameTable__ND5.h"
#include "VTop_Rename__WC5.h"
#include "VTop_TagBuffer.h"

// Other auxiliary header files
#include "VTop__Dpi.h"
#include "VTop__pch.h" // Precompiled header
#include "VTop__Syms.h"
2 changes: 1 addition & 1 deletion src/ExternalAXISim.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,7 @@ initial begin
end

// RTL sim input
logic inputAvail /*verilator public*/ = 0;
logic inputAvail /*verilator public*/ /* = 0 */;
logic[7:0] inputByte /*verilator public*/;

// Read Data Output
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6 changes: 3 additions & 3 deletions src/InstrDecoder.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -972,11 +972,11 @@ always_comb begin
uop.fu = FU_INT;

if (i32.fp.rm == 3'b000)
uop.opcode = INT_FSGNJ_S;
uop.opcode = /* INT_FSGNJ_S */ BM_FSGNJ_S;
else if (i32.fp.rm == 3'b001)
uop.opcode = INT_FSGNJN_S;
uop.opcode = /* INT_FSGNJN_S */ BM_FSGNJN_S;
else if (i32.fp.rm == 3'b010)
uop.opcode = INT_FSGNJX_S;
uop.opcode = /* INT_FSGNJX_S */ BM_FSGNJX_S;
else invalidEnc = 1;
end
5'b00101: begin
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4 changes: 2 additions & 2 deletions src/MemRTL.sv
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@mathis-s mathis-s Jan 24, 2026 •
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This should be better fixed by ignoring the warning instead of changing the code (also applies to all others)

Original file line number Diff line number Diff line change
Expand Up @@ -22,8 +22,8 @@ module MemRTL
(* ram_style = "block" *)
reg[WORD_SIZE-1:0] mem[NUM_WORDS-1:0] /* verilator public */;

reg ce_reg = 1;
reg ce1_reg = 1;
reg ce_reg /* = 1 */;
reg ce1_reg /* = 1 */;
reg we_reg;
reg[$clog2(NUM_WORDS)-1:0] addr_reg;
reg[$clog2(NUM_WORDS)-1:0] addr1_reg;
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2 changes: 1 addition & 1 deletion src/MemRTL1RW.sv
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Expand Up @@ -18,7 +18,7 @@ module MemRTL1RW
(* ram_style = "block" *)
reg[WORD_SIZE-1:0] mem[NUM_WORDS-1:0] /* verilator public */;

reg ce_reg = 1;
reg ce_reg /* = 1 */;
reg we_reg;
reg[$clog2(NUM_WORDS)-1:0] addr_reg;
reg[WORD_SIZE-1:0] data_reg;
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