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Fix initializing Macronix QSPI flashes with only 2 status registers #444

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Merged
merged 5 commits into from
Apr 8, 2025
Merged

Fix initializing Macronix QSPI flashes with only 2 status registers #444

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7fde9be
Fix initializing Macronix QSPI flashes with only 2 status registers
multiplemonomials Mar 31, 2025
90e6b8c
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multiplemonomials Apr 1, 2025
a2cddce
Set 4 byte addressing support to disabled to match comment
multiplemonomials Apr 1, 2025
078c1ec
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multiplemonomials Apr 1, 2025
b5d8f48
Missing break
multiplemonomials Apr 6, 2025
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10 changes: 7 additions & 3 deletions storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1113,12 +1113,16 @@ int QSPIFBlockDevice::_handle_vendor_quirks()
case 0xc2:
// Macronix devices have several quirks:
// 1. Have one status register and several config registers, with a nonstandard instruction for reading the config registers
// 2. Require setting a "fast mode" bit in config register 2 to operate at higher clock rates
// 3. Should never attempt to enable 4-byte addressing (it causes reads and writes to fail)
// 2. Require setting a "fast mode" bit in config register 2 to operate at higher clock rates (if config register 2 exists)
// 3. Should never attempt to enable 4-byte addressing (it causes reads and writes to fail). On MX25L12833F at least, the
// SFDP table claims to have 4-byte support but it actually does not!
tr_debug("Applying quirks for macronix");
_needs_fast_mode = true;
_num_status_registers = MBED_CONF_QSPI_MACRONIX_NUM_STATUS_REGISTER;
_read_status_reg_2_inst = QSPIF_INST_RDCR;
if (MBED_CONF_QSPI_MACRONIX_NUM_STATUS_REGISTER >= 3) {
_needs_fast_mode = true;
}
_attempt_4_byte_addressing = false;
break;
case 0x9d:
// ISSI devices have only one status register
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