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77 changes: 72 additions & 5 deletions targets/TARGET_STM/TARGET_STM32U0/clock_cfg/system_clock.c
Original file line number Diff line number Diff line change
Expand Up @@ -79,10 +79,77 @@ void SetSysClock(void)
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // TODO
MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
return 0; // FAIL
//return 1; // OK
/** HSE settings is prepared for values between 4MHz and <= 40MHz and must
* be divisible by either 4 or 5! Different values must be set manually.
*/
#if (HSE_VALUE < 4000000) || (HSE_VALUE > 40000000) && !((HSE_VALUE % 4000000 != 0) || (HSE_VALUE % 5000000 != 0))
#error HSE value must be >= 4MHz and <= 40MHz, and must be divisible by either 4 or 5!
#endif

RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

/** Configure the main internal regulator output voltage
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);

/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
if(bypass) {
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
} else {
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
}
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
if ((HSE_VALUE % 4000000 == 0) && (HSE_VALUE <= 32))
{
RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 4;
RCC_OscInitStruct.PLL.PLLN = 28;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 2;
RCC_OscInitStruct.PLL.PLLR = 2;
}
else if ((HSE_VALUE % 5000000 == 0) && (HSE_VALUE <= 40))
{
RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 5;
RCC_OscInitStruct.PLL.PLLN = 56;
RCC_OscInitStruct.PLL.PLLP = 5;
RCC_OscInitStruct.PLL.PLLQ = 5;
RCC_OscInitStruct.PLL.PLLR = 5;
}
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
return 0; // FAIL
}

/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{
return 0; // FAIL
}

#if DEVICE_USBDEVICE
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
return 0; // FAIL
}
#endif /* DEVICE_USBDEVICE */
return 1; // OK
}
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */

Expand All @@ -103,10 +170,10 @@ uint8_t SetSysClock_PLL_HSI(void)
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Expand Down
2 changes: 1 addition & 1 deletion targets/targets.json5
Original file line number Diff line number Diff line change
Expand Up @@ -4826,7 +4826,7 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
"MCU_STM32U083xC"
],
"overrides": {
"clock_source": "USE_PLL_HSI",
"clock_source": "USE_PLL_HSI", // Nucleo's default for the rest are necessary hardware changes
"lse_available": 1,
"default-adc-vref": 3.3
},
Expand Down