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Merged
merged 3 commits into from
Sep 4, 2025
Merged

Support NRF52840_DK in Mbed CE #492

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7654ff7
Able to flash code to nRF52840 DK!
multiplemonomials Sep 3, 2025
7e796e9
Update linker script to Mbed CE standard
multiplemonomials Sep 3, 2025
ea74da9
License fixes, few other tweaks
multiplemonomials Sep 3, 2025
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11 changes: 11 additions & 0 deletions targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/PeripheralPins.c
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Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
*/

#include "PeripheralPins.h"
Expand Down Expand Up @@ -67,6 +68,8 @@ const PinMap PinMap_I2C_testing[] = {
{P0_23, 0, 0},
{P0_24, 0, 0},
{P0_25, 0, 0},
{P0_26, 0, 0},
{P0_27, 0, 0},
{P0_28, 0, 0},
{P0_29, 0, 0},
{P0_30, 0, 0},
Expand Down Expand Up @@ -120,6 +123,8 @@ const PinMap PinMap_SPI_testing[] = {
{P0_23, 0, 0},
{P0_24, 0, 0},
{P0_25, 0, 0},
{P0_26, 0, 0},
{P0_27, 0, 0},
{P0_28, 0, 0},
{P0_29, 0, 0},
{P0_30, 0, 0},
Expand Down Expand Up @@ -173,6 +178,8 @@ const PinMap PinMap_UART_testing[] = {
{P0_23, 0, 0},
{P0_24, 0, 0},
{P0_25, 0, 0},
{P0_26, 0, 0},
{P0_27, 0, 0},
{P0_28, 0, 0},
{P0_29, 0, 0},
{P0_30, 0, 0},
Expand Down Expand Up @@ -226,6 +233,8 @@ const PinMap PinMap_PWM_testing[] = {
{P0_23, 0, 0},
{P0_24, 0, 0},
{P0_25, 0, 0},
{P0_26, 0, 0},
{P0_27, 0, 0},
{P0_28, 0, 0},
{P0_29, 0, 0},
{P0_30, 0, 0},
Expand Down Expand Up @@ -279,6 +288,8 @@ const PinMap PinMap_QSPI_testing[] = {
{P0_23, 0, 0},
{P0_24, 0, 0},
{P0_25, 0, 0},
{P0_26, 0, 0},
{P0_27, 0, 0},
{P0_28, 0, 0},
{P0_29, 0, 0},
{P0_30, 0, 0},
Expand Down
131 changes: 67 additions & 64 deletions ...TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_NRF52840_DK/PinNames.h
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Expand Up @@ -33,7 +33,8 @@
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
*/

/* MBED TARGET LIST: NRF52840_DK */
Expand Down Expand Up @@ -159,16 +160,6 @@ typedef enum {
p45 = P1_13,
p46 = P1_14,
p47 = P1_15,

LED1 = p13,
LED2 = p14,
LED3 = p15,
LED4 = p16,

BUTTON1 = p11,
BUTTON2 = p12,
BUTTON3 = p24,
BUTTON4 = p25,

RX_PIN_NUMBER = p8,
TX_PIN_NUMBER = p6,
Expand All @@ -191,69 +182,81 @@ typedef enum {
STDIO_UART_CTS = CTS_PIN_NUMBER,
STDIO_UART_RTS = RTS_PIN_NUMBER,

SPI_PSELMOSI0 = P1_13,
SPI_PSELMISO0 = P1_14,
SPI_PSELSS0 = P1_12,
SPI_PSELSCK0 = P1_15,
ARDUINO_UNO_D0 = P1_1,
ARDUINO_UNO_D1 = P1_2,
ARDUINO_UNO_D2 = P1_3,
ARDUINO_UNO_D3 = P1_4,
ARDUINO_UNO_D4 = P1_5,
ARDUINO_UNO_D5 = P1_6,
ARDUINO_UNO_D6 = P1_7,
ARDUINO_UNO_D7 = P1_8,

ARDUINO_UNO_D8 = P1_10,
ARDUINO_UNO_D9 = P1_11,
ARDUINO_UNO_D10 = P1_12,
ARDUINO_UNO_D11 = P1_13,
ARDUINO_UNO_D12 = P1_14,
ARDUINO_UNO_D13 = P1_15,

ARDUINO_UNO_D14 = p26,
ARDUINO_UNO_D15 = p27,

SPI_PSELMOSI1 = P1_2,
SPI_PSELMISO1 = P1_3,
SPI_PSELSS1 = P1_1,
SPI_PSELSCK1 = P1_4,
ARDUINO_UNO_A0 = p3,
ARDUINO_UNO_A1 = p4,
ARDUINO_UNO_A2 = p28,
ARDUINO_UNO_A3 = p29,
ARDUINO_UNO_A4 = p30,
ARDUINO_UNO_A5 = p31,

SPIS_PSELMOSI = P1_2,
SPIS_PSELMISO = P1_3,
SPIS_PSELSS = P1_1,
SPIS_PSELSCK = P1_4,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;

I2C_SDA0 = p26,
I2C_SCL0 = p27,
// LEDs and buttons
#define LED1 p13
#define LED2 p14
#define LED3 p15
#define LED4 p16

D0 = P1_1,
D1 = P1_2,
D2 = P1_3,
D3 = P1_4,
D4 = P1_5,
D5 = P1_6,
D6 = P1_7,
D7 = P1_8,
#define BUTTON1 p11
#define BUTTON2 p12
#define BUTTON3 p24
#define BUTTON4 p25

D8 = P1_10,
D9 = P1_11,
D10 = P1_12,
D11 = P1_13,
D12 = P1_14,
D13 = P1_15,
// Busses
#define I2C_SDA0 p26
#define I2C_SCL0 p27

D14 = p26,
D15 = p27,
#define SPI_PSELMOSI0 P1_13
#define SPI_PSELMISO0 P1_14
#define SPI_PSELSS0 P1_12
#define SPI_PSELSCK0 P1_15

A0 = p3,
A1 = p4,
A2 = p28,
A3 = p29,
A4 = p30,
A5 = p31,
#define SPI_PSELMOSI1 P1_2
#define SPI_PSELMISO1 P1_3
#define SPI_PSELSS1 P1_1
#define SPI_PSELSCK1 P1_4

/**** QSPI pins ****/
QSPI1_IO0 = P0_20,
QSPI1_IO1 = P0_21,
QSPI1_IO2 = P0_22,
QSPI1_IO3 = P0_23,
QSPI1_SCK = P0_19,
QSPI1_CSN = P0_17,
#define SPIS_PSELMOSI P1_2
#define SPIS_PSELMISO P1_3
#define SPIS_PSELSS P1_1
#define SPIS_PSELSCK P1_4

/**** QSPI FLASH pins ****/
QSPI_FLASH1_IO0 = QSPI1_IO0,
QSPI_FLASH1_IO1 = QSPI1_IO1,
QSPI_FLASH1_IO2 = QSPI1_IO2,
QSPI_FLASH1_IO3 = QSPI1_IO3,
QSPI_FLASH1_SCK = QSPI1_SCK,
QSPI_FLASH1_CSN = QSPI1_CSN,
/**** QSPI pins ****/
#define QSPI1_IO0 P0_20
#define QSPI1_IO1 P0_21
#define QSPI1_IO2 P0_22
#define QSPI1_IO3 P0_23
#define QSPI1_SCK P0_19
#define QSPI1_CSN P0_17

// Not connected
NC = (int)0xFFFFFFFF
} PinName;
/**** QSPI FLASH pins ****/
#define QSPI_FLASH1_IO0 QSPI1_IO0
#define QSPI_FLASH1_IO1 QSPI1_IO1
#define QSPI_FLASH1_IO2 QSPI1_IO2
#define QSPI_FLASH1_IO3 QSPI1_IO3
#define QSPI_FLASH1_SCK QSPI1_SCK
#define QSPI_FLASH1_CSN QSPI1_CSN

typedef enum {
PullNone = 0,
Expand Down
70 changes: 24 additions & 46 deletions ...NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld
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Expand Up @@ -16,42 +16,17 @@

/* Linker script to configure memory regions. */

/* Default to no softdevice */
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x0
#endif

#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x100000
#endif

#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#define MBED_RAM_SIZE 0x40000
#endif

#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x800
#endif

#define MBED_RAM0_START MBED_RAM_START
#define MBED_RAM0_SIZE 0x100

#define MBED_CRASH_REPORT_RAM_START (MBED_RAM0_START + MBED_RAM0_SIZE)
#define MBED_CRASH_REPORT_RAM_SIZE 0x100

#define MBED_RAM1_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - (MBED_RAM0_SIZE + MBED_CRASH_REPORT_RAM_SIZE))

MEMORY
{
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
RAM_NVIC (rwx) : ORIGIN = MBED_RAM0_START, LENGTH = MBED_RAM0_SIZE
RAM_CRASH_DATA (rwx) : ORIGIN = MBED_CRASH_REPORT_RAM_START, LENGTH = MBED_CRASH_REPORT_RAM_SIZE
RAM (rwx) : ORIGIN = MBED_RAM1_START, LENGTH = MBED_RAM1_SIZE
FLASH (rx) : ORIGIN = MBED_CONFIGURED_ROM_BANK_IROM1_START, LENGTH = MBED_CONFIGURED_ROM_BANK_IROM1_SIZE
RAM (rwx) : ORIGIN = MBED_RAM_BANK_IRAM1_START, LENGTH = MBED_RAM_BANK_IRAM1_SIZE
}


OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")

/* Linker script to place sections and symbol values. Should be used together
Expand Down Expand Up @@ -84,6 +59,28 @@ ENTRY(Reset_Handler)

SECTIONS
{
/* RAM vector table */
.nvictable (NOLOAD) :
{
PROVIDE(__start_nvictable = .);
KEEP(*(.nvictable))
PROVIDE(__stop_nvictable = .);
} > RAM

/* Crash data RAM (preserved across resets) */
.crash_data_ram (NOLOAD):
{
. = ALIGN(8);
__CRASH_DATA_RAM__ = .;
__CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */
. += MBED_CRASH_REPORT_RAM_SIZE;
__CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */

/* Include any used-defined data in the crash data RAM */
KEEP(*(.keep.crash_data_ram))
*(.m_crash_data_ram)
} > RAM

.text :
{
KEEP(*(.Vectors))
Expand Down Expand Up @@ -201,25 +198,6 @@ SECTIONS

__edata = .;

.nvictable (NOLOAD) :
{
PROVIDE(__start_nvictable = .);
KEEP(*(.nvictable))
PROVIDE(__stop_nvictable = .);
} > RAM_NVIC

.crash_data_ram :
{
. = ALIGN(8);
__CRASH_DATA_RAM__ = .;
__CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */
KEEP(*(.keep.crash_data_ram))
*(.m_crash_data_ram) /* This is a user defined section */
. += MBED_CRASH_REPORT_RAM_SIZE;
. = ALIGN(8);
__CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */
} > RAM_CRASH_DATA

.noinit (NOLOAD) :
{
PROVIDE(__start_noinit = .);
Expand Down
15 changes: 1 addition & 14 deletions targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/cmsis_nvic.h
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Expand Up @@ -3,6 +3,7 @@
*******************************************************************************
* Copyright (c) 2016 ARM Limited. All rights reserved.
* All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
Expand Down Expand Up @@ -35,20 +36,6 @@
#define NVIC_NUM_VECTORS (16 + 48) // CORE + MCU Peripherals
#define NVIC_USER_IRQ_OFFSET 16

// RAM size defines, same as in the linker script
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x0
#endif

#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x100000
#endif

#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#define MBED_RAM_SIZE 0x40000
#endif

#include "nrf.h"
#include "cmsis.h"

Expand Down
5 changes: 4 additions & 1 deletion targets/targets.json5
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Expand Up @@ -7472,7 +7472,7 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
},
"NRF52840_DK": {
"supported_form_factors": [
"ARDUINO"
"ARDUINO_UNO"
],
"inherits": [
"MCU_NRF52840"
Expand All @@ -7492,6 +7492,9 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
"supported_application_profiles": [
"full", "bare-metal"
],
"components_add": [
"QSPIF"
],
"image_url": "https://www.nordicsemi.com/-/media/Images/Products/DevKits/nRF52-Series/nRF52840-DK/nRF52840-DK/nRF52840-DK-prod-page.png?h=750&iar=0&mw=350&w=350&hash=3DB140F6AE70CAE159FD911D8E6E9109"
},
"ARDUINO_NANO33BLE": {
Expand Down
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