A hardware-implemented JPEG encoder for efficient lossy image compression using SystemVerilog.
- Fully synthesizable SystemVerilog implementation of JPEG encoder modules
- Includes DCT, Quantization, and Huffman Encoding blocks
- Modular architecture for Y, Cb, and Cr component processing
- Verified using Cocotb testbenches with Python golden models
- Supports pipeline optimization and byte-stuffing handling
git clone https://github.com/YourUsername/JPEG-Encoder.git
cd JPEG-EncoderFirst do this:
cd sdkTo compress an image, simply run:
run.bat| Category | Description | Location |
|---|---|---|
| Documentation | ReadTheDocs Project Page | ReadTheDocs |
| Simulations | All testbenches | tests/ directory |
| Modules | Each core block (DCT, Quantizer, Huffman, FIFO) | rtl/ directory |
| License | Project's license file | LICENSE |
For detailed module descriptions, timing diagrams, and verification results, visit:
Full Documentation on ReadTheDocs
Developed at the (MEDS), UET Lahore.

