[autoWS][FA] Add vectorization and fadd2_reduce #540
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Summary: mark N_CTX constexpr Test Plan: Reviewers: Subscribers: Tasks: Tags:
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| else: | ||
| m_ij = tl.maximum(m_i, tl.max(qk, 1) * qk_scale) | ||
| qk = qk * qk_scale - m_ij[:, None] | ||
| if VECT_MUL == 2 or VECT_MUL == 3: |
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Any reason not to test the bits directly?
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| if VECT_MUL == 2 or VECT_MUL == 3: | |
| if VECT_MUL & 2: |
| p0, p1 = p.reshape([PM, 2, PN // 2]).permute(0, 2, 1).split() | ||
| l_ij0, l_ij1 = tl.reduce((p0, p1), axis=1, combine_fn=_reduce_fadd2) | ||
| l_i0 = l_i0 * alpha + l_ij0 | ||
| l_i1 = l_i1 * alpha + l_ij1 |
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Can we sum them after doing the reduction so we can keep the same interface? (and keep the differences localised to this part of the program)
Would that also save a register?
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You mean "l_ij = l_ij0 + l_ij1" then a single l_i = l_i * alpha + l_ij? That is a good point.
The advantage is removing one addition inside the loop vs. register pressure of l_i1.
I basically copied from Gluon. And this is what is implemented in the dp version as well.
We can potentially clean this up if the alternative is better.
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Summary: mark N_CTX constexpr
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