Merge branch 'tc-l3' into dev

Author: maksyuki

rtl/.scalafmt.conf

@@ -24,15 +24,6 @@ align.tokens.add = [
   },
   {
     code = "="
-  },
-  {
-    code = "&&"
-  },
-  {
-    code = "||"
-  },
-    {
-    code = "==="
   }
 ]
 

rtl/tc_l3/src/main/scala/common/AXI4Config.scala

@@ -0,0 +1,18 @@
+package treecorel2
+
+import chisel3._
+import chisel3.util._
+
+trait AXI4Config extends IOConfig {
+  val AxiProtLen   = 3
+  val AxiIdLen     = 4
+  val AxiUserLen   = 1
+  val AxiSizeLen   = 3
+  val AxiLen       = 8
+  val AxiStrb      = 8
+  val AxiBurstLen  = 2
+  val AxiCacheLen  = 4
+  val AxiQosLen    = 4
+  val AxiRegionLen = 4
+  val AxiRespLen   = 2
+}

rtl/tc_l3/src/main/scala/common/InstConfig.scala

@@ -0,0 +1,39 @@
+package treecorel2
+
+import chisel3._
+import chisel3.util._
+
+trait IOConfig {
+  val XLen       = 64
+  val InstLen    = 32
+  val RegfileLen = 5
+  val RegfileNum = 1 << RegfileLen
+  val ISALen     = 6
+  // branch prediction
+  val GHRLen    = 5
+  val PHTSize   = 1 << GHRLen
+  val BTBIdxLen = 5
+  val BTBPcLen  = XLen - BTBIdxLen
+  val BTBTgtLen = XLen
+  val BTBSize   = 1 << BTBIdxLen
+}
+
+trait InstConfig extends IOConfig {
+  val SoCEna   = true
+  val CacheEna = false
+
+  // cache
+  val NWay          = 4
+  val NBank         = 4
+  val NSet          = 32
+  val CacheLineSize = XLen * NBank
+  val ICacheSize    = NWay * NSet * CacheLineSize
+  val DCacheSize    = NWay * NSet * CacheLineSize
+
+  // clint
+  val ClintBaseAddr  = 0x02000000.U(XLen.W)
+  val ClintBoundAddr = 0x0200bfff.U(XLen.W)
+  val MSipOffset     = 0x0.U(XLen.W)
+  val MTimeOffset    = 0xbff8.U(XLen.W)
+  val MTimeCmpOffset = 0x4000.U(XLen.W)
+}

rtl/tc_l3/src/main/scala/core/Axi.scala

@@ -227,13 +227,13 @@ class CSR(implicit val p: Parameters) extends Module {
   io.out := Lookup(csr_addr, 0.U, csrFile).asUInt
 
   val privValid = csr_addr(9, 8) <= PRV
-  val privInst  = io.cmd               === CSR.P
-  val isEcall   = privInst              && !csr_addr(0) && !csr_addr(8)
-  val isEbreak  = privInst              && csr_addr(0)  && !csr_addr(8)
-  val isEret    = privInst              && !csr_addr(0) && csr_addr(8)
+  val privInst  = io.cmd === CSR.P
+  val isEcall   = privInst && !csr_addr(0) && !csr_addr(8)
+  val isEbreak  = privInst && csr_addr(0) && !csr_addr(8)
+  val isEret    = privInst && !csr_addr(0) && csr_addr(8)
   val csrValid  = csrFile.map(_._1 === csr_addr).reduce(_ || _)
-  val csrRO     = csr_addr(11, 10).andR || csr_addr    === CSR.mtvec || csr_addr === CSR.mtdeleg
-  val wen       = io.cmd               === CSR.W        || io.cmd(1) && rs1_addr.orR
+  val csrRO     = csr_addr(11, 10).andR || csr_addr === CSR.mtvec || csr_addr === CSR.mtdeleg
+  val wen       = io.cmd === CSR.W || io.cmd(1) && rs1_addr.orR
   val wdata = MuxLookup(
     io.cmd,
     0.U,
@@ -264,10 +264,10 @@ class CSR(implicit val p: Parameters) extends Module {
   )
 
   io.expt := io.illegal || iaddrInvalid || laddrInvalid || saddrInvalid ||
-    io.cmd(1, 0).orR && (!csrValid  || !privValid) || wen && csrRO ||
-    (privInst        && !privValid) || isEcall     || isEbreak
-  io.evec            := mtvec + (PRV << 6)
-  io.epc             := mepc
+    io.cmd(1, 0).orR && (!csrValid || !privValid) || wen && csrRO ||
+    (privInst && !privValid) || isEcall || isEbreak
+  io.evec := mtvec + (PRV << 6)
+  io.epc  := mepc
 
   // Counters
   time := time + 1.U