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maksyukimaksyuki
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refactor: add common inst config
1 parent 30adc75 commit 4c1143a

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4 files changed

+155
-154
lines changed

4 files changed

+155
-154
lines changed

‎rtl/tc_l3/src/main/scala/common/InstConfig.scala‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,9 @@ trait IOConfig {
2121
trait InstConfig extends IOConfig {
2222
val SoCEna = true
2323
val CacheEna = false
24-
24+
// fetch
25+
val FlashStartAddr = "h0000000030000000".U(XLen.W)
26+
val DiffStartAddr = "h0000000080000000".U(XLen.W)
2527
// cache
2628
val NWay = 4
2729
val NBank = 4

‎rtl/tc_l3/src/main/scala/core/CSR.scala‎

Lines changed: 74 additions & 75 deletions
Original file line numberDiff line numberDiff line change
@@ -97,102 +97,100 @@ object Cause {
9797
val Ecall = 0x8.U
9898
}
9999

100-
class CSRIO(implicit p: Parameters) extends Bundle {
100+
class CSRIO extends Bundle with IOConfig {
101101
val stall = Input(Bool())
102102
val cmd = Input(UInt(3.W))
103-
val in = Input(UInt(xlen.W))
104-
val out = Output(UInt(xlen.W))
103+
val in = Input(UInt(XLen.W))
104+
val out = Output(UInt(XLen.W))
105105
// excpetion
106-
val pc = Input(UInt(xlen.W))
107-
val addr = Input(UInt(xlen.W))
108-
val inst = Input(UInt(xlen.W))
106+
val pc = Input(UInt(XLen.W))
107+
val addr = Input(UInt(XLen.W))
108+
val inst = Input(UInt(XLen.W))
109109
val illegal = Input(Bool())
110110
val st_type = Input(UInt(2.W))
111111
val ld_type = Input(UInt(3.W))
112112
val pc_check = Input(Bool())
113113
val expt = Output(Bool())
114-
val evec = Output(UInt(xlen.W))
115-
val epc = Output(UInt(xlen.W))
114+
val evec = Output(UInt(XLen.W))
115+
val epc = Output(UInt(XLen.W))
116116
// HTIF
117117
val host = new HostIO
118118
}
119119

120-
class CSR(implicit val p: Parameters) extends Module {
120+
class CSR extends Module with InstConfig {
121121
val io = IO(new CSRIO)
122122

123-
val csr_addr = io.inst(31, 20)
124-
val rs1_addr = io.inst(19, 15)
123+
protected val csr_addr = io.inst(31, 20)
124+
protected val rs1_addr = io.inst(19, 15)
125125

126126
// user counters
127-
val time = RegInit(0.U(xlen.W))
128-
val timeh = RegInit(0.U(xlen.W))
129-
val cycle = RegInit(0.U(xlen.W))
130-
val cycleh = RegInit(0.U(xlen.W))
131-
val instret = RegInit(0.U(xlen.W))
132-
val instreth = RegInit(0.U(xlen.W))
127+
protected val time = RegInit(0.U(XLen.W))
128+
protected val timeh = RegInit(0.U(XLen.W))
129+
protected val cycle = RegInit(0.U(XLen.W))
130+
protected val cycleh = RegInit(0.U(XLen.W))
131+
protected val instret = RegInit(0.U(XLen.W))
132+
protected val instreth = RegInit(0.U(XLen.W))
133133

134-
val mcpuid = Cat(
134+
protected val mcpuid = Cat(
135135
0.U(2.W) /* RV32I */,
136-
0.U((xlen - 28).W),
136+
0.U((XLen - 28).W),
137137
(1 << ('I' - 'A') /* Base ISA */ |
138138
1 << ('U' - 'A') /* User Mode */ ).U(26.W)
139139
)
140-
val mimpid = 0.U(xlen.W) // not implemented
141-
val mhartid = 0.U(xlen.W) // only one hart
140+
protected val mimpid = 0.U(XLen.W) // not implemented
141+
protected val mhartid = 0.U(XLen.W) // only one hart
142142

143143
// interrupt enable stack
144-
val PRV = RegInit(CSR.PRV_M)
145-
val PRV1 = RegInit(CSR.PRV_M)
146-
val PRV2 = 0.U(2.W)
147-
val PRV3 = 0.U(2.W)
148-
val IE = RegInit(false.B)
149-
val IE1 = RegInit(false.B)
150-
val IE2 = false.B
151-
val IE3 = false.B
144+
protected val PRV = RegInit(CSR.PRV_M)
145+
protected val PRV1 = RegInit(CSR.PRV_M)
146+
protected val PRV2 = 0.U(2.W)
147+
protected val PRV3 = 0.U(2.W)
148+
protected val IE = RegInit(false.B)
149+
protected val IE1 = RegInit(false.B)
150+
protected val IE2 = false.B
151+
protected val IE3 = false.B
152152
// virtualization management field
153-
val VM = 0.U(5.W)
153+
protected val VM = 0.U(5.W)
154154
// memory privilege
155-
val MPRV = false.B
155+
protected val MPRV = false.B
156156
// extention context status
157-
val XS = 0.U(2.W)
158-
val FS = 0.U(2.W)
159-
val SD = 0.U(1.W)
160-
val mstatus = Cat(SD, 0.U((xlen - 23).W), VM, MPRV, XS, FS, PRV3, IE3, PRV2, IE2, PRV1, IE1, PRV, IE)
161-
val mtvec = Const.PC_EVEC.U(xlen.W)
162-
val mtdeleg = 0x0.U(xlen.W)
157+
protected val XS = 0.U(2.W)
158+
protected val FS = 0.U(2.W)
159+
protected val SD = 0.U(1.W)
160+
protected val mstatus = Cat(SD, 0.U((XLen - 23).W), VM, MPRV, XS, FS, PRV3, IE3, PRV2, IE2, PRV1, IE1, PRV, IE)
161+
protected val mtvec = Const.PC_EVEC.U(XLen.W) // TODO:
162+
protected val mtdeleg = 0x0.U(XLen.W)
163163

164164
// interrupt registers
165-
val MTIP = RegInit(false.B)
166-
val HTIP = false.B
167-
val STIP = false.B
168-
val MTIE = RegInit(false.B)
169-
val HTIE = false.B
170-
val STIE = false.B
171-
val MSIP = RegInit(false.B)
172-
val HSIP = false.B
173-
val SSIP = false.B
174-
val MSIE = RegInit(false.B)
175-
val HSIE = false.B
176-
val SSIE = false.B
177-
val mip = Cat(0.U((xlen - 8).W), MTIP, HTIP, STIP, false.B, MSIP, HSIP, SSIP, false.B)
178-
val mie = Cat(0.U((xlen - 8).W), MTIE, HTIE, STIE, false.B, MSIE, HSIE, SSIE, false.B)
165+
protected val MTIP = RegInit(false.B)
166+
protected val HTIP = false.B
167+
protected val STIP = false.B
168+
protected val MTIE = RegInit(false.B)
169+
protected val HTIE = false.B
170+
protected val STIE = false.B
171+
protected val MSIP = RegInit(false.B)
172+
protected val HSIP = false.B
173+
protected val SSIP = false.B
174+
protected val MSIE = RegInit(false.B)
175+
protected val HSIE = false.B
176+
protected val SSIE = false.B
177+
protected val mip = Cat(0.U((XLen - 8).W), MTIP, HTIP, STIP, false.B, MSIP, HSIP, SSIP, false.B)
178+
protected val mie = Cat(0.U((XLen - 8).W), MTIE, HTIE, STIE, false.B, MSIE, HSIE, SSIE, false.B)
179179

180-
val mtimecmp = Reg(UInt(xlen.W))
180+
protected val mtimecmp = Reg(UInt(XLen.W))
181+
protected val mscratch = Reg(UInt(XLen.W))
182+
protected val mepc = Reg(UInt(XLen.W))
183+
protected val mcause = Reg(UInt(XLen.W))
184+
protected val mbadaddr = Reg(UInt(XLen.W))
185+
protected val mtohost = RegInit(0.U(XLen.W))
186+
protected val mfromhost = Reg(UInt(XLen.W))
181187

182-
val mscratch = Reg(UInt(xlen.W))
183-
184-
val mepc = Reg(UInt(xlen.W))
185-
val mcause = Reg(UInt(xlen.W))
186-
val mbadaddr = Reg(UInt(xlen.W))
187-
188-
val mtohost = RegInit(0.U(xlen.W))
189-
val mfromhost = Reg(UInt(xlen.W))
190188
io.host.tohost := mtohost
191189
when(io.host.fromhost.valid) {
192190
mfromhost := io.host.fromhost.bits
193191
}
194192

195-
val csrFile = Seq(
193+
protected val csrFile = Seq(
196194
BitPat(CSR.cycle) -> cycle,
197195
BitPat(CSR.time) -> time,
198196
BitPat(CSR.instret) -> instret,
@@ -226,15 +224,15 @@ class CSR(implicit val p: Parameters) extends Module {
226224

227225
io.out := Lookup(csr_addr, 0.U, csrFile).asUInt
228226

229-
val privValid = csr_addr(9, 8) <= PRV
230-
val privInst = io.cmd === CSR.P
231-
val isEcall = privInst && !csr_addr(0) && !csr_addr(8)
232-
val isEbreak = privInst && csr_addr(0) && !csr_addr(8)
233-
val isEret = privInst && !csr_addr(0) && csr_addr(8)
234-
val csrValid = csrFile.map(_._1 === csr_addr).reduce(_ || _)
235-
val csrRO = csr_addr(11, 10).andR || csr_addr === CSR.mtvec || csr_addr === CSR.mtdeleg
236-
val wen = io.cmd === CSR.W || io.cmd(1) && rs1_addr.orR
237-
val wdata = MuxLookup(
227+
protected val privValid = csr_addr(9, 8) <= PRV
228+
protected val privInst = io.cmd === CSR.P
229+
protected val isEcall = privInst && !csr_addr(0) && !csr_addr(8)
230+
protected val isEbreak = privInst && csr_addr(0) && !csr_addr(8)
231+
protected val isEret = privInst && !csr_addr(0) && csr_addr(8)
232+
protected val csrValid = csrFile.map(_._1 === csr_addr).reduce(_ || _)
233+
protected val csrRO = csr_addr(11, 10).andR || csr_addr === CSR.mtvec || csr_addr === CSR.mtdeleg
234+
protected val wen = io.cmd === CSR.W || io.cmd(1) && rs1_addr.orR
235+
protected val wdata = MuxLookup(
238236
io.cmd,
239237
0.U,
240238
Seq(
@@ -243,8 +241,9 @@ class CSR(implicit val p: Parameters) extends Module {
243241
CSR.C -> (io.out & ~io.in)
244242
)
245243
)
246-
val iaddrInvalid = io.pc_check && io.addr(1)
247-
val laddrInvalid = MuxLookup(
244+
245+
protected val iaddrInvalid = io.pc_check && io.addr(1)
246+
protected val laddrInvalid = MuxLookup(
248247
io.ld_type,
249248
false.B,
250249
Seq(
@@ -254,7 +253,7 @@ class CSR(implicit val p: Parameters) extends Module {
254253
)
255254
)
256255

257-
val saddrInvalid = MuxLookup(
256+
protected val saddrInvalid = MuxLookup(
258257
io.st_type,
259258
false.B,
260259
Seq(
@@ -274,7 +273,7 @@ class CSR(implicit val p: Parameters) extends Module {
274273
when(time.andR) { timeh := timeh + 1.U }
275274
cycle := cycle + 1.U
276275
when(cycle.andR) { cycleh := cycleh + 1.U }
277-
val isInstRet = io.inst =/= Instructions.NOP && (!io.expt || isEcall || isEbreak) && !io.stall
276+
protected val isInstRet = io.inst =/= Instructions.NOP && (!io.expt || isEcall || isEbreak) && !io.stall
278277
when(isInstRet) { instret := instret + 1.U }
279278
when(isInstRet && instret.andR) { instreth := instreth + 1.U }
280279

@@ -317,7 +316,7 @@ class CSR(implicit val p: Parameters) extends Module {
317316
.elsewhen(csr_addr === CSR.mtimecmp) { mtimecmp := wdata }
318317
.elsewhen(csr_addr === CSR.mscratch) { mscratch := wdata }
319318
.elsewhen(csr_addr === CSR.mepc) { mepc := wdata >> 2.U << 2.U }
320-
.elsewhen(csr_addr === CSR.mcause) { mcause := wdata & (BigInt(1) << (xlen - 1) | 0xf).U }
319+
.elsewhen(csr_addr === CSR.mcause) { mcause := wdata & (BigInt(1) << (XLen - 1) | 0xf).U }
321320
.elsewhen(csr_addr === CSR.mbadaddr) { mbadaddr := wdata }
322321
.elsewhen(csr_addr === CSR.mtohost) { mtohost := wdata }
323322
.elsewhen(csr_addr === CSR.mfromhost) { mfromhost := wdata }

‎rtl/tc_l3/src/main/scala/core/Core.scala‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -3,21 +3,21 @@ package treecorel3
33
import chisel._
44
import chisel.uitl._
55

6-
class HostIO(implicit p: Parameters) extends Bundle {
7-
val fromhost = Flipped(Valid(UInt(xlen.W)))
8-
val tohost = Output(UInt(xlen.W))
6+
class HostIO extends Bundle with IOConfig {
7+
val fromhost = Flipped(Valid(UInt(XLen.W)))
8+
val tohost = Output(UInt(XLen.W))
99
}
1010

11-
class CoreIO(implicit p: Parameters) extends Bundle {
11+
class CoreIO extends Bundle {
1212
val host = new HostIO
13-
val icache = Flipped((new CacheIO))
14-
val dcache = Flipped((new CacheIO))
13+
val icache = Flipped(new CacheIO)
14+
val dcache = Flipped(new CacheIO)
1515
}
1616

17-
class Core(implicit val p: Parameters) extends Module {
18-
val io = IO(new CoreIO)
19-
val dpath = Module(new DataPath)
20-
val ctrl = Module(new Control)
17+
class Core extends Module {
18+
val io = IO(new CoreIO)
19+
protected val dpath = Module(new DataPath)
20+
protected val ctrl = Module(new Control)
2121

2222
io.icache <> dpath.io.icache
2323
io.dcache <> dpath.io.dcache

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