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maksyukimaksyuki
committed
style: remove unused wires
1 parent 9d22b2b commit 6fe2b62

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5 files changed

+56
-81
lines changed

5 files changed

+56
-81
lines changed

‎rtl/tc_l2/src/main/scala/common/InstConfig.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ trait InstConfig {
118118
val MTimeOffset = 0xbff8.U(XLen.W)
119119
val MTimeCmpOffset = 0x4000.U(XLen.W)
120120
// csr addr
121-
val CSRAddrLen = 12
121+
val CSRAddrLen = 12
122122
val mhartidAddr = 0xf14.U(CSRAddrLen.W)
123123
val mstatusAddr = 0x300.U(CSRAddrLen.W)
124124
val mieAddr = 0x304.U(CSRAddrLen.W)

‎rtl/tc_l2/src/main/scala/core/id/IDU.scala‎

Lines changed: 9 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -15,22 +15,14 @@ class IDU extends Module with InstConfig {
1515
val gpr = Output(Vec(RegfileNum, UInt(XLen.W)))
1616
})
1717

18-
protected val idReg = RegEnable(io.if2id, WireInit(0.U.asTypeOf(new IF2IDIO())), io.globalEn)
19-
protected val valid = idReg.valid
20-
protected val inst = idReg.inst
21-
protected val pc = idReg.pc
22-
protected val branIdx = idReg.branIdx
23-
protected val predTaken = idReg.predTaken
24-
18+
protected val idReg = RegEnable(io.if2id, WireInit(0.U.asTypeOf(new IF2IDIO())), io.globalEn)
19+
protected val inst = idReg.inst
2520
protected val rs1 = inst(19, 15)
2621
protected val rs2 = inst(24, 20)
2722
protected val wdest = inst(11, 7)
2823

2924
protected val decoder = Module(new ISADecoder)
3025
decoder.io.inst := inst
31-
protected val isa = decoder.io.isa
32-
protected val imm = decoder.io.imm
33-
protected val wen = decoder.io.wen
3426

3527
protected val regfile = new RegFile
3628
protected val src1En = io.wbdata.wen && (rs1 === io.wbdata.wdest) && (rs1 =/= 0.U)
@@ -42,16 +34,16 @@ class IDU extends Module with InstConfig {
4234
regfile.write(io.wbdata.wen, io.wbdata.wdest, io.wbdata.data)
4335
}
4436

45-
io.id2ex.valid := Mux(io.stall, false.B, valid)
37+
io.id2ex.valid := Mux(io.stall, false.B, idReg.valid)
4638
io.id2ex.inst := inst
47-
io.id2ex.pc := pc
48-
io.id2ex.branIdx := branIdx
49-
io.id2ex.predTaken := predTaken
50-
io.id2ex.isa := isa
39+
io.id2ex.pc := idReg.pc
40+
io.id2ex.branIdx := idReg.branIdx
41+
io.id2ex.predTaken := idReg.predTaken
5142
io.id2ex.src1 := src1
5243
io.id2ex.src2 := src2
53-
io.id2ex.imm := imm
54-
io.id2ex.wen := wen
44+
io.id2ex.isa := decoder.io.isa
45+
io.id2ex.imm := decoder.io.imm
46+
io.id2ex.wen := decoder.io.wen
5547
io.id2ex.wdest := wdest
5648
io.gpr := regfile.gpr
5749
}

‎rtl/tc_l2/src/main/scala/core/if/IFU.scala‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ package treecorel2
33
import chisel3._
44
import chisel3.util._
55

6-
import treecorel2.common.{ConstVal, InstConfig}
6+
import treecorel2.common.InstConfig
77

88
class IFU extends Module with InstConfig {
99
val io = IO(new Bundle {
@@ -19,7 +19,6 @@ class IFU extends Module with InstConfig {
1919
protected val startAddr = Mux(io.socEn, FlashStartAddr, SimStartAddr)
2020
protected val pc = RegInit(startAddr)
2121
protected val valid = Mux(reset.asBool(), false.B, true.B)
22-
protected val inst = io.fetch.data
2322

2423
protected val bpu = Module(new BPU)
2524
bpu.io.branchInfo <> io.branchInfo
@@ -40,7 +39,7 @@ class IFU extends Module with InstConfig {
4039
}
4140

4241
io.if2id.valid := Mux(io.stall, false.B, valid)
43-
io.if2id.inst := inst
42+
io.if2id.inst := io.fetch.data
4443
io.if2id.pc := pc
4544
io.if2id.branIdx := bpu.io.predIdx
4645
io.if2id.predTaken := bpu.io.predTaken

‎rtl/tc_l2/src/main/scala/core/ma/MAU.scala‎

Lines changed: 12 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -14,19 +14,14 @@ class MAU extends Module {
1414
val mtip = Output(Bool())
1515
})
1616

17-
protected val memReg = RegEnable(io.ex2mem, WireInit(0.U.asTypeOf(new EX2MEMIO())), io.globalEn)
18-
protected val valid = memReg.valid
19-
protected val inst = memReg.inst
20-
protected val pc = memReg.pc
21-
protected val branIdx = memReg.branIdx
22-
protected val predTaken = memReg.predTaken
23-
protected val isa = memReg.isa
24-
protected val imm = memReg.imm
25-
protected val rs1 = memReg.inst(19, 15)
26-
protected val rs2 = memReg.inst(24, 20)
27-
protected val src1 = memReg.src1
28-
protected val src2 = memReg.src2
29-
protected val csr = memReg.csr
17+
protected val memReg = RegEnable(io.ex2mem, WireInit(0.U.asTypeOf(new EX2MEMIO())), io.globalEn)
18+
protected val valid = memReg.valid
19+
protected val inst = memReg.inst
20+
protected val isa = memReg.isa
21+
protected val imm = memReg.imm
22+
protected val src1 = memReg.src1
23+
protected val src2 = memReg.src2
24+
protected val csr = memReg.csr
3025

3126
protected val lsu = Module(new LSU)
3227
lsu.io.valid := valid
@@ -53,9 +48,9 @@ class MAU extends Module {
5348

5449
io.mem2wb.valid := valid
5550
io.mem2wb.inst := inst
56-
io.mem2wb.pc := pc
57-
io.mem2wb.branIdx := branIdx
58-
io.mem2wb.predTaken := predTaken
51+
io.mem2wb.pc := memReg.pc
52+
io.mem2wb.branIdx := memReg.branIdx
53+
io.mem2wb.predTaken := memReg.predTaken
5954
io.mem2wb.isa := isa
6055
io.mem2wb.src1 := src1
6156
io.mem2wb.src2 := src2
@@ -72,6 +67,6 @@ class MAU extends Module {
7267
io.mem2wb.cvalid := clint.io.cvalid
7368
io.mem2wb.timeIntrEn := memReg.timeIntrEn
7469
io.mem2wb.ecallEn := memReg.ecallEn
75-
io.mem2wb.csr := csr
70+
io.mem2wb.csr := memReg.csr
7671
io.mtip := clint.io.mtip
7772
}

‎rtl/tc_l2/src/main/scala/core/wb/WBU.scala‎

Lines changed: 32 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -21,21 +21,15 @@ class WBU extends Module with InstConfig {
2121
protected val inst = wbReg.inst
2222
protected val pc = wbReg.pc
2323
protected val isa = wbReg.isa
24-
protected val src1 = wbReg.src1
25-
protected val src2 = wbReg.src2
26-
protected val imm = wbReg.imm
2724
protected val wen = wbReg.wen
2825
protected val wdest = wbReg.wdest
2926
protected val aluRes = wbReg.aluRes
30-
protected val branch = wbReg.branch
31-
protected val tgt = wbReg.tgt
3227
protected val link = wbReg.link
3328
protected val auipc = wbReg.auipc
3429
protected val loadData = wbReg.loadData
3530
protected val csrData = wbReg.csrData
3631
protected val cvalid = wbReg.cvalid
3732
protected val timeIntrEn = wbReg.timeIntrEn
38-
protected val ecallEn = wbReg.ecallEn
3933
protected val csr = wbReg.csr
4034

4135
protected val wbdata = aluRes | link | auipc | loadData | csrData
@@ -73,24 +67,22 @@ class WBU extends Module with InstConfig {
7367
cycleCnt.inc()
7468
when(io.globalEn && valid) { instrCnt.inc() }
7569

76-
instComm.io.clock := clock
77-
instComm.io.coreid := 0.U
78-
instComm.io.index := 0.U
79-
instComm.io.valid := diffValid && ~timeIntrEnReg
80-
instComm.io.pc := RegEnable(pc, 0.U, io.globalEn)
81-
instComm.io.instr := RegEnable(inst, 0.U, io.globalEn)
82-
instComm.io.special := 0.U
83-
instComm.io.skip := diffValid && RegEnable(printVis || mcycleVis || mmioEn || mipVis, false.B, io.globalEn)
84-
instComm.io.isRVC := false.B
85-
instComm.io.scFailed := false.B
86-
instComm.io.wen := RegEnable(wen, false.B, io.globalEn)
87-
instComm.io.wdata := RegEnable(wbdata, 0.U, io.globalEn)
88-
instComm.io.wdest := RegEnable(wdest, 0.U, io.globalEn)
89-
90-
archIntRegState.io.clock := clock
91-
archIntRegState.io.coreid := 0.U
92-
archIntRegState.io.gpr := io.gpr
93-
70+
instComm.io.clock := clock
71+
instComm.io.coreid := 0.U
72+
instComm.io.index := 0.U
73+
instComm.io.valid := diffValid && ~timeIntrEnReg
74+
instComm.io.pc := RegEnable(pc, 0.U, io.globalEn)
75+
instComm.io.instr := RegEnable(inst, 0.U, io.globalEn)
76+
instComm.io.special := 0.U
77+
instComm.io.skip := diffValid && RegEnable(printVis || mcycleVis || mmioEn || mipVis, false.B, io.globalEn)
78+
instComm.io.isRVC := false.B
79+
instComm.io.scFailed := false.B
80+
instComm.io.wen := RegEnable(wen, false.B, io.globalEn)
81+
instComm.io.wdata := RegEnable(wbdata, 0.U, io.globalEn)
82+
instComm.io.wdest := RegEnable(wdest, 0.U, io.globalEn)
83+
archIntRegState.io.clock := clock
84+
archIntRegState.io.coreid := 0.U
85+
archIntRegState.io.gpr := io.gpr
9486
csrState.io.clock := clock
9587
csrState.io.coreid := 0.U
9688
csrState.io.mstatus := csr.mstatus
@@ -111,24 +103,21 @@ class WBU extends Module with InstConfig {
111103
csrState.io.mtvec := csr.mtvec
112104
csrState.io.stvec := 0.U
113105
csrState.io.priviledgeMode := 3.U
114-
115-
archEvt.io.clock := clock
116-
archEvt.io.coreid := 0.U
117-
archEvt.io.intrNO := Mux(diffValid && timeIntrEnReg, 7.U, 0.U)
118-
archEvt.io.cause := 0.U
119-
archEvt.io.exceptionPC := RegEnable(pc, 0.U, io.globalEn)
120-
archEvt.io.exceptionInst := RegEnable(inst, 0.U, io.globalEn)
121-
122-
trapEvt.io.clock := clock
123-
trapEvt.io.coreid := 0.U
124-
trapEvt.io.valid := diffValid && RegEnable(haltVis, false.B, io.globalEn)
125-
trapEvt.io.code := io.gpr(10)(7, 0)
126-
trapEvt.io.pc := RegEnable(pc, 0.U, io.globalEn)
127-
trapEvt.io.cycleCnt := cycleCnt.value
128-
trapEvt.io.instrCnt := instrCnt.value
129-
130-
archFpRegState.io.clock := clock
131-
archFpRegState.io.coreid := 0.U
132-
archFpRegState.io.fpr := RegInit(VecInit(Seq.fill(RegfileNum)(0.U(XLen.W))))
106+
archEvt.io.clock := clock
107+
archEvt.io.coreid := 0.U
108+
archEvt.io.intrNO := Mux(diffValid && timeIntrEnReg, 7.U, 0.U)
109+
archEvt.io.cause := 0.U
110+
archEvt.io.exceptionPC := RegEnable(pc, 0.U, io.globalEn)
111+
archEvt.io.exceptionInst := RegEnable(inst, 0.U, io.globalEn)
112+
trapEvt.io.clock := clock
113+
trapEvt.io.coreid := 0.U
114+
trapEvt.io.valid := diffValid && RegEnable(haltVis, false.B, io.globalEn)
115+
trapEvt.io.code := io.gpr(10)(7, 0)
116+
trapEvt.io.pc := RegEnable(pc, 0.U, io.globalEn)
117+
trapEvt.io.cycleCnt := cycleCnt.value
118+
trapEvt.io.instrCnt := instrCnt.value
119+
archFpRegState.io.clock := clock
120+
archFpRegState.io.coreid := 0.U
121+
archFpRegState.io.fpr := RegInit(VecInit(Seq.fill(RegfileNum)(0.U(XLen.W))))
133122
}
134123
}

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