refactor: move csr and clint const addr to instconfig

Author: maksyuki

rtl/tc_l2/src/main/scala/common/ConstVal.scala

@@ -7,24 +7,4 @@ object ConstVal {
   // addr width
   val AddrLen      = 64
   val AddrAlignLen = log2Ceil(AddrLen / 8)
-
-  val CSRAddrLen   = 12
-  val CLINTAddrLen = 64
-  // csr addr
-  val mhartidAddr  = 0xf14.U(CSRAddrLen.W)
-  val mstatusAddr  = 0x300.U(CSRAddrLen.W)
-  val mieAddr      = 0x304.U(CSRAddrLen.W)
-  val mtvecAddr    = 0x305.U(CSRAddrLen.W)
-  val mscratchAddr = 0x340.U(CSRAddrLen.W)
-  val mepcAddr     = 0x341.U(CSRAddrLen.W)
-  val mcauseAddr   = 0x342.U(CSRAddrLen.W)
-  val mipAddr      = 0x344.U(CSRAddrLen.W)
-  val mcycleAddr   = 0xb00.U(CSRAddrLen.W)
-  val medelegAddr  = 0x302.U(CSRAddrLen.W)
-
-  val ClintBaseAddr  = 0x02000000.U(CLINTAddrLen.W)
-  val ClintBoundAddr = 0x0200bfff.U(CLINTAddrLen.W)
-  val MSipOffset     = 0x0.U(CLINTAddrLen.W)
-  val MTimeOffset    = 0xbff8.U(CLINTAddrLen.W)
-  val MTimeCmpOffset = 0x4000.U(CLINTAddrLen.W)
 }

rtl/tc_l2/src/main/scala/common/InstConfig.scala

@@ -110,4 +110,23 @@ trait InstConfig {
   val CacheLineSize = XLen * NBank
   val ICacheSize    = NWay * NSet * CacheLineSize
   val DCacheSize    = NWay * NSet * CacheLineSize
+
+  // clint
+  val ClintBaseAddr  = 0x02000000.U(XLen.W)
+  val ClintBoundAddr = 0x0200bfff.U(XLen.W)
+  val MSipOffset     = 0x0.U(XLen.W)
+  val MTimeOffset    = 0xbff8.U(XLen.W)
+  val MTimeCmpOffset = 0x4000.U(XLen.W)
+  // csr addr
+  val CSRAddrLen = 12
+  val mhartidAddr  = 0xf14.U(CSRAddrLen.W)
+  val mstatusAddr  = 0x300.U(CSRAddrLen.W)
+  val mieAddr      = 0x304.U(CSRAddrLen.W)
+  val mtvecAddr    = 0x305.U(CSRAddrLen.W)
+  val mscratchAddr = 0x340.U(CSRAddrLen.W)
+  val mepcAddr     = 0x341.U(CSRAddrLen.W)
+  val mcauseAddr   = 0x342.U(CSRAddrLen.W)
+  val mipAddr      = 0x344.U(CSRAddrLen.W)
+  val mcycleAddr   = 0xb00.U(CSRAddrLen.W)
+  val medelegAddr  = 0x302.U(CSRAddrLen.W)
 }

rtl/tc_l2/src/main/scala/core/exec/CSRReg.scala

@@ -47,16 +47,16 @@ class CSRReg extends Module with InstConfig {
   protected val medeleg  = RegInit(0.U(XLen.W))
   protected val mhartid  = RegInit(0.U(XLen.W))
 
-  protected val mhartidVis  = addr === ConstVal.mhartidAddr
-  protected val mstatusVis  = addr === ConstVal.mstatusAddr
-  protected val mieVis      = addr === ConstVal.mieAddr
-  protected val mtvecVis    = addr === ConstVal.mtvecAddr
-  protected val mscratchVis = addr === ConstVal.mscratchAddr
-  protected val mepcVis     = addr === ConstVal.mepcAddr
-  protected val mcauseVis   = addr === ConstVal.mcauseAddr
-  protected val mipVis      = addr === ConstVal.mipAddr
-  protected val mcycleVis   = addr === ConstVal.mcycleAddr
-  protected val medelegVis  = addr === ConstVal.medelegAddr
+  protected val mhartidVis  = addr === mhartidAddr
+  protected val mstatusVis  = addr === mstatusAddr
+  protected val mieVis      = addr === mieAddr
+  protected val mtvecVis    = addr === mtvecAddr
+  protected val mscratchVis = addr === mscratchAddr
+  protected val mepcVis     = addr === mepcAddr
+  protected val mcauseVis   = addr === mcauseAddr
+  protected val mipVis      = addr === mipAddr
+  protected val mcycleVis   = addr === mcycleAddr
+  protected val medelegVis  = addr === medelegAddr
 
   protected val mcycleVal   = Mux(csrVis && mcycleVis, mcycle, 0.U)
   protected val mstatusVal  = Mux(csrVis && mstatusVis, mstatus, 0.U)

rtl/tc_l2/src/main/scala/core/ma/CLINT.scala

@@ -18,8 +18,8 @@ class CLINT extends Module with InstConfig {
 
   protected val addr        = Mux(io.cld.en, io.cld.addr(31, 0), 0.U) | Mux(io.csd.en, io.csd.addr(31, 0), 0.U)
   protected val wdata       = io.csd.data
-  protected val mtimeVis    = addr === ConstVal.ClintBaseAddr + ConstVal.MTimeOffset
-  protected val mtimecmpVis = addr === ConstVal.ClintBaseAddr + ConstVal.MTimeCmpOffset
+  protected val mtimeVis    = addr === ClintBaseAddr + MTimeOffset
+  protected val mtimecmpVis = addr === ClintBaseAddr + MTimeCmpOffset
 
   // check if a mmio access
   protected val cren   = io.cld.en && (mtimecmpVis || mtimeVis) && io.valid

rtl/tc_l2/src/main/scala/core/wb/WBU.scala

@@ -57,8 +57,8 @@ class WBU extends Module with InstConfig {
   if (!SoCEna) {
     val mmioEn        = cvalid
     val csrVis        = (isa === instCSRRW) || (isa === instCSRRS) || (isa === instCSRRC) || (isa === instCSRRWI) || (isa === instCSRRSI) || (isa === instCSRRCI)
-    val mcycleVis     = csrVis && (inst(31, 20) === ConstVal.mcycleAddr)
-    val mipVis        = csrVis && (inst(31, 20) === ConstVal.mipAddr)
+    val mcycleVis     = csrVis && (inst(31, 20) === mcycleAddr)
+    val mipVis        = csrVis && (inst(31, 20) === mipAddr)
     val timeIntrEnReg = RegEnable(timeIntrEn, false.B, io.globalEn)
     val diffValid     = io.globalEn && (RegEnable(valid, false.B, io.globalEn) || timeIntrEnReg)