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@@ -33,16 +33,19 @@ Season 1 was a first educational practice which aimed to design riscv processor
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Unlike Season 1, Season 2 had eleven undergraduates from five universities to design processors, and it is the first attempt to promote this project to the other university.
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### Season 3[**2021.7-2022.1**]: More students(One hundred students), More open source tools(NEMU, difftest, AM...)
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TreeCore project is the achievement of this season. Season 3 now is completed, and the official website is [ysyx.org](https://ysyx.org/).
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TreeCoreL1[[1]](#id_tcl1) and TreeCoreL2[[2]](#id_tcl2) are the achievement of this season. After about six months of development, TreeCoreL2 obtained the qualification of tape-out in second shuttle. You can visit the official website [ysyx.org](https://ysyx.org/) to get more information.
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> NOTE: The PCB card with TreeCoreL2 possible return in the second quarter of 2022, so on board debugging cannot release now.
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### Season 4[**2022.2.20-2022.8.31, in progress**]: More open source IPs(SDRAM, VGA...), Smoother learning curve(bbs, tutorials, lecture, ...)
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TreeCoreL3[[3]](#id_tcl3) and TreeCoreL4[[4]](#id_tcl4) will be the expected achievement of this season.
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Now the TreeCore has two version: TreeCoreL1(**_TreeCore Learning 1_**) and TreeCoreL2(**_TreeCore Learning 2_**). The TreeCore project aims to help students to learn how to write riscv processors by themselves with **step-to-step materials**. Not like textbooks only exhibit all of concepts in one time, the learn process of TreeCore is incremental. That means TreeCore only provides a very simple model with necessary new knowledges you need to learn first, then add extra codes to modify the whole design.
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> NOTE: now the TreeCoreL2 is under tape-out phase. The chip debug and test introduction will release soon.
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## Motivation
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I heard the word '**_riscv_**' first time in sophomore year(that is, the summer of 2016). My roommate participated in the pilot class of **_Computer Architecture_**, and their final assignment was to **design a simple soft-core riscv processor**. At that time, I only knew it was an open source RISC ISA launched by the UC, Berkeley. What is unexpected to me is that just after a few period of time, the riscv has been supported by many semiconductor giants and research institutions. Although the performance of riscv are still limited now, **I believe riscv will usher in a revolution that can change the old pattern in someday**.
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The best way to learn the processor design is to implement it from scratch. When I searched online and found the learning threshold and cost is very high. In addition, in order to pursue high performance, some open-source riscv cores are very complex(such as using dynamics branch prediction, multi-core processing, out-of-order execution technology, etc), these are very difficult for beginners to learn. So I decided to design a series of open source processors from scratch, which has **simple, understandable architecture, high-quality code with step-to-step tutorial**.
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The best way to learn the processor design is to implement it from scratch. When I searched online and found the learning threshold is very high. In addition, in order to pursue high performance, some open-source riscv cores are very complex(such as using dynamics branch prediction, multi-core processing, out-of-order execution technology, etc), these are very difficult for beginners to learn. So I decided to design a series of open source processors from scratch, which has **simple, understandable architecture, high-quality code with step-to-step tutorial**.
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I hope it can become a ABC project like Arduino to make more processor enthusiasts and computer related specialized students enter into the computer architecture field. In the future, under the mutual promotion of the software and hardware ecosystem, I believe more people will like processor design and be willing to spend time on it.
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**intro** the plan with the such as the target every type core need to meet. and timeline
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**TreeCoreL1**
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**TreeCoreL1**<spanid="id_tcl1"></span>
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* 64-bits FSM
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* written by chisel3
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In fact, TreeCoreL1 is not just a processor, it only supplies the basic implement of Turing machine model: 'loop + '.
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In fact, TreeCoreL1 is not a processor, it is a bundle of some independent verilator programs and common chisel modules writing for learning.
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#### Configuration
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## Usage
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This section introduces how to set up development environment and runs unit test for your own riscv processor.
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This section introduces how to set up development environment and runs unit test for your own riscv processor. Project directory is:
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```bash
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env ->
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| hello_world_tb.gtkw # gtkwave wave config
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| hello_world_tb.sh # compile script
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| hello_world_tb.v # hello world verilog module
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fpga ->
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| bare_metal/ # bare metal verilog module for fpga
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report ->
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| tc_l2.md # treecore l2 wiki
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rtl ->
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| Makefile # main Makefile for rtl test
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| scripts/ # tool scripts called from main Makefile
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| build.sc # chisel config
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| tc_l(x)[1, 2, 3] # rtl project
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tests ->
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| compile_rtl.py # bare metal module compile script
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| compliance_test.py # isa compliance test
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| run_all_isa_test.py # run all isa test
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tools ->
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| bin2mem.py # convert bin file to mem file
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| bin2mif.py # convert bin file to mif file
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```
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### Enviroment Setup
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> NOTE: All of the components and tools are installed under linux operation system. To gurantee the compatibility and stability, I strongly recommend using `ubuntu 20.04 LTS`. `ubuntu 18.04` and `ubuntu 16.04` is not supported official.
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First, you need to install verilator, mill and dependency libraries:
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If you're new to TreeCore project, we suggest you start with the install section. Remeber you **ONLY** need to install the below libraries once.
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> NOTE: In order to download and configure all libraries successful, you **NEED**
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First, you need to install verilator, mill, difftest, abstract-machine and other dependency libraries:
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