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maksyukimaksyuki
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Merge branch 'tc-l3' into dev
2 parents 56aac23 + 65044d3 commit c458e31

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10 files changed

+683
-5
lines changed

10 files changed

+683
-5
lines changed

‎rtl/Makefile‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ SHELL=/bin/bash
22

33
# be carefully, this path will be used in clean(rm -rf)!!!
44
# need to set the $(CHIP_TARGET) with tc_lx(2, 3, 4...)
5-
CHIP_TARGET := tc_l2
5+
CHIP_TARGET := tc_l3
66
ROOT_PATH := $(shell pwd)/dependency
77
SOURCE_PATH := $(ROOT_PATH)/../$(CHIP_TARGET)
88
BUILD_DIR := $(SOURCE_PATH)/build
@@ -92,7 +92,7 @@ template:
9292

9393
###### chisel target ######
9494
millTest:
95-
mill -i __.test
95+
mill -i $(CHIP_TARGET).test
9696

9797
chiselBuild:
9898
mkdir -p $(BUILD_DIR)
@@ -102,16 +102,16 @@ chiselHelp:
102102
mill -i $(CHIP_TARGET).runMain top.TopMain --help
103103

104104
millCompile:
105-
mill -i __.compile
105+
mill -i $(CHIP_TARGET).compile
106106

107107
millBsp:
108108
mill -i mill.bsp.BSP/install
109109

110110
format:
111-
mill -i __.reformat
111+
mill -i $(CHIP_TARGET).reformat
112112

113113
checkformat:
114-
mill -i __.checkFormat
114+
mill -i $(CHIP_TARGET).checkFormat
115115

116116
###### NEMU target ######
117117
nemuBuild:

‎rtl/build.sc‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,34 @@ object tc_l2 extends ScalaModule with ScalafmtModule { m =>
3232
override def moduleDeps = super.moduleDeps ++ Seq(difftest)
3333
}
3434

35+
object tc_l3 extends ScalaModule with ScalafmtModule { m =>
36+
override def scalaVersion = "2.12.13"
37+
override def scalacOptions = Seq(
38+
"-Xsource:2.11",
39+
"-language:reflectiveCalls",
40+
"-deprecation",
41+
"-feature",
42+
"-Xcheckinit",
43+
// Enables autoclonetype2 in 3.4.x (on by default in 3.5)
44+
"-P:chiselplugin:useBundlePlugin"
45+
)
46+
override def ivyDeps = Agg(
47+
ivy"edu.berkeley.cs::chisel3:3.4.3",
48+
)
49+
override def scalacPluginIvyDeps = Agg(
50+
ivy"edu.berkeley.cs:::chisel3-plugin:3.4.3",
51+
ivy"org.scalamacros:::paradise:2.1.1"
52+
)
53+
object test extends Tests with Utest {
54+
override def ivyDeps = m.ivyDeps() ++ Agg(
55+
ivy"com.lihaoyi::utest:0.7.10",
56+
ivy"edu.berkeley.cs::chiseltest:0.3.3",
57+
)
58+
}
59+
60+
override def moduleDeps = super.moduleDeps ++ Seq(difftest)
61+
}
62+
3563
object difftest extends ScalaModule {
3664
override def scalaVersion = "2.12.13"
3765
override def millSourcePath = os.pwd / "dependency" / "difftest"

‎rtl/tc_l3/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
sim-verilog:

‎rtl/tc_l3/src/main/scala/core/ALU.scala‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
package treecorel3
2+
3+
import chisel._
4+
import chisel.uitl._
5+
6+
object ALU {
7+
val ALUOperLen = 4
8+
val ALU_ADD = 0.U(ALUOperLen.W)
9+
val ALU_SUB = 1.U(ALUOperLen.W)
10+
val ALU_AND = 2.U(ALUOperLen.W)
11+
val ALU_OR = 3.U(ALUOperLen.W)
12+
val ALU_XOR = 4.U(ALUOperLen.W)
13+
val ALU_SLT = 5.U(ALUOperLen.W)
14+
val ALU_SLL = 6.U(ALUOperLen.W)
15+
val ALU_SLTU = 7.U(ALUOperLen.W)
16+
val ALU_SRL = 8.U(ALUOperLen.W)
17+
val ALU_SRA = 9.U(ALUOperLen.W)
18+
val ALU_COPY_A = 10.U(ALUOperLen.W)
19+
val ALU_COPY_B = 11.U(ALUOperLen.W)
20+
val ALU_XXX = 15.U(ALUOperLen.W)
21+
}

‎rtl/tc_l3/src/main/scala/core/CSR.scala‎

Lines changed: 89 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
1+
package treecorel3
2+
3+
import chisel._
4+
import chisel.uitl._
5+
6+
object CSR {
7+
val CSRTypeLen = 3
8+
val N = 0.U(CSRTypeLen.W)
9+
val W = 1.U(CSRTypeLen.W)
10+
val S = 2.U(CSRTypeLen.W)
11+
val C = 3.U(CSRTypeLen.W)
12+
val P = 4.U(CSRTypeLen.W)
13+
14+
// Supports machine & user modes
15+
val PRV_U = 0x0.U(2.W)
16+
val PRV_M = 0x3.U(2.W)
17+
18+
// User-level CSR addrs
19+
val cycle = 0xc00.U(12.W)
20+
val time = 0xc01.U(12.W)
21+
val instret = 0xc02.U(12.W)
22+
val cycleh = 0xc80.U(12.W)
23+
val timeh = 0xc81.U(12.W)
24+
val instreth = 0xc82.U(12.W)
25+
26+
// Supervisor-level CSR addrs
27+
val cyclew = 0x900.U(12.W)
28+
val timew = 0x901.U(12.W)
29+
val instretw = 0x902.U(12.W)
30+
val cyclehw = 0x980.U(12.W)
31+
val timehw = 0x981.U(12.W)
32+
val instrethw = 0x982.U(12.W)
33+
34+
// Machine-level CSR addrs
35+
// Machine Information Registers
36+
val mcpuid = 0xf00.U(12.W)
37+
val mimpid = 0xf01.U(12.W)
38+
val mhartid = 0xf10.U(12.W)
39+
// Machine Trap Setup
40+
val mstatus = 0x300.U(12.W)
41+
val mtvec = 0x301.U(12.W)
42+
val mtdeleg = 0x302.U(12.W)
43+
val mie = 0x304.U(12.W)
44+
val mtimecmp = 0x321.U(12.W)
45+
// Machine Timers and Counters
46+
val mtime = 0x701.U(12.W)
47+
val mtimeh = 0x741.U(12.W)
48+
// Machine Trap Handling
49+
val mscratch = 0x340.U(12.W)
50+
val mepc = 0x341.U(12.W)
51+
val mcause = 0x342.U(12.W)
52+
val mbadaddr = 0x343.U(12.W)
53+
val mip = 0x344.U(12.W)
54+
// Machine HITF
55+
val mtohost = 0x780.U(12.W)
56+
val mfromhost = 0x781.U(12.W)
57+
58+
val regs = List(
59+
cycle,
60+
time,
61+
instret,
62+
cycleh,
63+
timeh,
64+
instreth,
65+
cyclew,
66+
timew,
67+
instretw,
68+
cyclehw,
69+
timehw,
70+
instrethw,
71+
mcpuid,
72+
mimpid,
73+
mhartid,
74+
mtvec,
75+
mtdeleg,
76+
mie,
77+
mtimecmp,
78+
mtime,
79+
mtimeh,
80+
mscratch,
81+
mepc,
82+
mcause,
83+
mbadaddr,
84+
mip,
85+
mtohost,
86+
mfromhost,
87+
mstatus
88+
)
89+
}

‎rtl/tc_l3/src/main/scala/core/Control.scala‎

Lines changed: 159 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,159 @@
1+
package treecorel3
2+
3+
import chisel._
4+
import chisel.uitl._
5+
6+
object Control {
7+
val Y = true.B
8+
val F = false.B
9+
10+
val PCTypeLen = 2
11+
val PC_0 = 0.U(PCTypeLen.W)
12+
val PC_4 = 1.U(PCTypeLen.W)
13+
val PC_ALU = 2.U(PCTypeLen.W)
14+
val PC_EPC = 3.U(PCTypeLen.W)
15+
16+
val OprandTypeLen = 1
17+
val A_XXX = 0.U(OprandTypeLen.W)
18+
val A_PC = 1.U(OprandTypeLen.W)
19+
val A_RS1 = 2.U(OprandTypeLen.W)
20+
val B_XXX = 0.U(OprandTypeLen.W)
21+
val B_PC = 1.U(OprandTypeLen.W)
22+
val B_RS1 = 2.U(OprandTypeLen.W)
23+
24+
val IMMTypeLen = 3
25+
val IMM_X = 0.U(IMMTypeLen.W)
26+
val IMM_I = 1.U(IMMTypeLen.W)
27+
val IMM_S = 2.U(IMMTypeLen.W)
28+
val IMM_U = 3.U(IMMTypeLen.W)
29+
val IMM_J = 4.U(IMMTypeLen.W)
30+
val IMM_B = 5.U(IMMTypeLen.W)
31+
val IMM_Z = 6.U(IMMTypeLen.W)
32+
33+
val BranchTypeLen = 3
34+
val BR_XXX = 0.U(BranchTypeLen.W)
35+
val BR_LTU = 1.U(BranchTypeLen.W)
36+
val BR_LT = 2.U(BranchTypeLen.W)
37+
val BR_EQ = 3.U(BranchTypeLen.W)
38+
val BR_GEU = 4.U(BranchTypeLen.W)
39+
val BR_GE = 5.U(BranchTypeLen.W)
40+
val BR_NE = 6.U(BranchTypeLen.W)
41+
42+
val StoreTypeLen = 2
43+
val ST_XXX = 0.U(StoreTypeLen.W)
44+
val ST_SW = 1.U(StoreTypeLen.W)
45+
val ST_SH = 2.U(StoreTypeLen.W)
46+
val ST_SB = 3.U(StoreTypeLen.W)
47+
48+
val LoadTypeLen = 3
49+
val LD_XXX = 0.U(LoadTypeLen.W)
50+
val LD_LW = 1.U(LoadTypeLen.W)
51+
val LD_LH = 2.U(LoadTypeLen.W)
52+
val LD_LB = 3.U(LoadTypeLen.W)
53+
val LD_LHU = 4.U(LoadTypeLen.W)
54+
val LD_LBU = 5.U(LoadTypeLen.W)
55+
56+
val WbTypeLen = 2
57+
val WB_ALU = 0.U(WbTypeLen.W)
58+
val WB_MEM = 1.U(WbTypeLen.W)
59+
val WB_PC4 = 2.U(WbTypeLen.W)
60+
val WB_CSR = 3.U(WbTypeLen.W)
61+
62+
// kill wb_en illegal?
63+
// pc_sel a_sel b_sel imm_sel alu_op br_type | st_type ld_type wb_sel | csr_cmd |
64+
// | | | | | | | | | | | | |
65+
val defRes = List(PC_4, A_XXX, B_XXX, IMM_X, ALU_XXX, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, Y)
66+
67+
val map = Array(
68+
LUI -> List(PC_4, A_PC, B_IMM, IMM_U, ALU_COPY_B, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
69+
AUIPC -> List(PC_4, A_PC, B_IMM, IMM_U, ALU_ADD, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
70+
JAL -> List(PC_ALU, A_PC, B_IMM, IMM_J, ALU_ADD, BR_XXX, Y, ST_XXX, LD_XXX, WB_PC4, Y, CSR.N, N),
71+
JALR -> List(PC_ALU, A_RS1, B_IMM, IMM_I, ALU_ADD, BR_XXX, Y, ST_XXX, LD_XXX, WB_PC4, Y, CSR.N, N),
72+
BEQ -> List(PC_4, A_PC, B_IMM, IMM_B, ALU_ADD, BR_EQ, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),
73+
BNE -> List(PC_4, A_PC, B_IMM, IMM_B, ALU_ADD, BR_NE, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),
74+
BLT -> List(PC_4, A_PC, B_IMM, IMM_B, ALU_ADD, BR_LT, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),
75+
BGE -> List(PC_4, A_PC, B_IMM, IMM_B, ALU_ADD, BR_GE, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),
76+
BLTU -> List(PC_4, A_PC, B_IMM, IMM_B, ALU_ADD, BR_LTU, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),
77+
BGEU -> List(PC_4, A_PC, B_IMM, IMM_B, ALU_ADD, BR_GEU, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),
78+
LB -> List(PC_0, A_RS1, B_IMM, IMM_I, ALU_ADD, BR_XXX, Y, ST_XXX, LD_LB, WB_MEM, Y, CSR.N, N),
79+
LH -> List(PC_0, A_RS1, B_IMM, IMM_I, ALU_ADD, BR_XXX, Y, ST_XXX, LD_LH, WB_MEM, Y, CSR.N, N),
80+
LW -> List(PC_0, A_RS1, B_IMM, IMM_I, ALU_ADD, BR_XXX, Y, ST_XXX, LD_LW, WB_MEM, Y, CSR.N, N),
81+
LBU -> List(PC_0, A_RS1, B_IMM, IMM_I, ALU_ADD, BR_XXX, Y, ST_XXX, LD_LBU, WB_MEM, Y, CSR.N, N),
82+
LHU -> List(PC_0, A_RS1, B_IMM, IMM_I, ALU_ADD, BR_XXX, Y, ST_XXX, LD_LHU, WB_MEM, Y, CSR.N, N),
83+
SB -> List(PC_4, A_RS1, B_IMM, IMM_S, ALU_ADD, BR_XXX, N, ST_SB, LD_XXX, WB_ALU, N, CSR.N, N),
84+
SH -> List(PC_4, A_RS1, B_IMM, IMM_S, ALU_ADD, BR_XXX, N, ST_SH, LD_XXX, WB_ALU, N, CSR.N, N),
85+
SW -> List(PC_4, A_RS1, B_IMM, IMM_S, ALU_ADD, BR_XXX, N, ST_SW, LD_XXX, WB_ALU, N, CSR.N, N),
86+
ADDI -> List(PC_4, A_RS1, B_IMM, IMM_I, ALU_ADD, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
87+
SLTI -> List(PC_4, A_RS1, B_IMM, IMM_I, ALU_SLT, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
88+
SLTIU -> List(PC_4, A_RS1, B_IMM, IMM_I, ALU_SLTU, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
89+
XORI -> List(PC_4, A_RS1, B_IMM, IMM_I, ALU_XOR, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
90+
ORI -> List(PC_4, A_RS1, B_IMM, IMM_I, ALU_OR, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
91+
ANDI -> List(PC_4, A_RS1, B_IMM, IMM_I, ALU_AND, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
92+
SLLI -> List(PC_4, A_RS1, B_IMM, IMM_I, ALU_SLL, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
93+
SRLI -> List(PC_4, A_RS1, B_IMM, IMM_I, ALU_SRL, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
94+
SRAI -> List(PC_4, A_RS1, B_IMM, IMM_I, ALU_SRA, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
95+
ADD -> List(PC_4, A_RS1, B_RS2, IMM_X, ALU_ADD, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
96+
SUB -> List(PC_4, A_RS1, B_RS2, IMM_X, ALU_SUB, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
97+
SLL -> List(PC_4, A_RS1, B_RS2, IMM_X, ALU_SLL, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
98+
SLT -> List(PC_4, A_RS1, B_RS2, IMM_X, ALU_SLT, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
99+
SLTU -> List(PC_4, A_RS1, B_RS2, IMM_X, ALU_SLTU, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
100+
XOR -> List(PC_4, A_RS1, B_RS2, IMM_X, ALU_XOR, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
101+
SRL -> List(PC_4, A_RS1, B_RS2, IMM_X, ALU_SRL, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
102+
SRA -> List(PC_4, A_RS1, B_RS2, IMM_X, ALU_SRA, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
103+
OR -> List(PC_4, A_RS1, B_RS2, IMM_X, ALU_OR, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
104+
AND -> List(PC_4, A_RS1, B_RS2, IMM_X, ALU_AND, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),
105+
FENCE -> List(PC_4, A_XXX, B_XXX, IMM_X, ALU_XXX, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),
106+
FENCEI -> List(PC_0, A_XXX, B_XXX, IMM_X, ALU_XXX, BR_XXX, Y, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),
107+
CSRRW -> List(PC_0, A_RS1, B_XXX, IMM_X, ALU_COPY_A, BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.W, N),
108+
CSRRS -> List(PC_0, A_RS1, B_XXX, IMM_X, ALU_COPY_A, BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.S, N),
109+
CSRRC -> List(PC_0, A_RS1, B_XXX, IMM_X, ALU_COPY_A, BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.C, N),
110+
CSRRWI -> List(PC_0, A_XXX, B_XXX, IMM_Z, ALU_XXX, BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.W, N),
111+
CSRRSI -> List(PC_0, A_XXX, B_XXX, IMM_Z, ALU_XXX, BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.S, N),
112+
CSRRCI -> List(PC_0, A_XXX, B_XXX, IMM_Z, ALU_XXX, BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.C, N),
113+
ECALL -> List(PC_4, A_XXX, B_XXX, IMM_X, ALU_XXX, BR_XXX, N, ST_XXX, LD_XXX, WB_CSR, N, CSR.P, N),
114+
EBREAK -> List(PC_4, A_XXX, B_XXX, IMM_X, ALU_XXX, BR_XXX, N, ST_XXX, LD_XXX, WB_CSR, N, CSR.P, N),
115+
ERET -> List(PC_EPC, A_XXX, B_XXX, IMM_X, ALU_XXX, BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, N, CSR.P, N),
116+
WFI -> List(PC_4, A_XXX, B_XXX, IMM_X, ALU_XXX, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N)
117+
)
118+
}
119+
120+
class ControlIO(implicit p: Parameters) extends Bundle {
121+
val inst = Input(UInt(xlen.W))
122+
val pc_sel = Output(UInt(2.W))
123+
val inst_kill = Output(Bool())
124+
val a_sel = Output(UInt(1.W))
125+
val b_sel = Output(UInt(1.W))
126+
val imm_sel = Output(UInt(3.W))
127+
val alu_op = Output(UInt(4.W))
128+
val br_type = Output(UInt(3.W))
129+
val st_type = Output(UInt(2.W))
130+
val ld_type = Output(UInt(3.W))
131+
val wb_sel = Output(UInt(2.W))
132+
val wb_en = Output(Bool())
133+
val csr_cmd = Output(UInt(3.W))
134+
val illegal = Output(Bool())
135+
}
136+
137+
class Control(implicit p: Parameters) extends Module {
138+
val io = IO(new ControlIO)
139+
val decRes = ListLookup(io.inst, Control.defRes, Control.map)
140+
141+
// Control signals for Fetch
142+
io.pc_sel := decRes(0)
143+
io.inst_kill := decRes(6)
144+
145+
// Control signals for Execute
146+
io.a_sel := decRes(1)
147+
io.b_sel := decRes(2)
148+
io.imm_sel := decRes(3)
149+
io.alu_op := decRes(4)
150+
io.br_type := decRes(5)
151+
io.st_type := decRes(7)
152+
153+
// Control signals for Write Back
154+
io.ld_type := decRes(8)
155+
io.wb_sel := decRes(9)
156+
io.wb_en := decRes(10)
157+
io.csr_cmd := decRes(11)
158+
io.illegal := decRes(12)
159+
}

‎rtl/tc_l3/src/main/scala/core/Core.scala‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
package treecorel3
2+
3+
import chisel._
4+
import chisel.uitl._
5+
6+
class HostIO(implicit p: Parameters) extends Bundle {
7+
val fromhost = Flipped(Valid(UInt(xlen.W)))
8+
val tohost = Output(UInt(xlen.W))
9+
}
10+
11+
class CoreIO(implicit p: Parameters) extends Bundle {
12+
val host = new HostIO
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val icache = Flipped((new CacheIO))
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val dcache = Flipped((new CacheIO))
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}
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class Core(implicit val p: Parameters) extends Module {
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val io = IO(new CoreIO)
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val dpath = Module(new DataPath)
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val ctrl = Module(new Control)
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io.icache <> dpath.io.icache
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io.dcache <> dpath.io.dcache
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ctrl.io <> dpath.io.ctrl
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}

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