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maksyukimaksyuki
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refactor: add inst wt en decoder
1 parent 7b8a2cf commit d4718a9

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4 files changed

+69
-81
lines changed

4 files changed

+69
-81
lines changed

‎rtl/tc_l2/src/main/scala/common/InstConfig.scala‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,8 @@ trait InstConfig {
2929
val bInstType = 4.U(InstTypeLen.W)
3030
val uInstType = 5.U(InstTypeLen.W)
3131
val jInstType = 6.U(InstTypeLen.W)
32+
val wtRegTrue = true.B
33+
val wtRegFalse = false.B
3234

3335
val NWay = 4
3436
val NBank = 4

‎rtl/tc_l2/src/main/scala/core/exec/ACU.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ class AGU extends Module {
2121
protected val val1Reg = RegInit(0.U(64.W))
2222
protected val val2Reg = RegInit(0.U(64.W))
2323
protected val busyReg = RegInit(false.B)
24-
protected val gcdVis = io.isa.GCD
24+
protected val gcdVis = false.B
2525

2626
when(gcdVis && !busyReg) {
2727
val1Reg := io.src1

‎rtl/tc_l2/src/main/scala/core/id/ISADecoder.scala‎

Lines changed: 66 additions & 79 deletions
Original file line numberDiff line numberDiff line change
@@ -195,103 +195,90 @@ class ISADecoder extends Module with InstConfig {
195195
io.isa.REMU := (io.inst === BitPat("b0000001_?????_?????_111_?????_0110011"))
196196
io.isa.REMUW := (io.inst === BitPat("b0000001_?????_?????_111_?????_0111011"))
197197
io.isa.REMW := (io.inst === BitPat("b0000001_?????_?????_110_?????_0111011"))
198-
io.isa.GCD := (io.inst === BitPat("b0000000_?????_?????_000_?????_0001000"))
199198

200-
protected val arith = io.isa.ADD || io.isa.ADDW || io.isa.ADDI || io.isa.ADDIW || io.isa.SUB || io.isa.SUBW || io.isa.LUI || io.isa.AUIPC
201-
protected val logc = io.isa.XOR || io.isa.XORI || io.isa.OR || io.isa.ORI || io.isa.AND || io.isa.ANDI
202-
protected val shift = io.isa.SLL || io.isa.SLLI || io.isa.SLLW || io.isa.SLLIW || io.isa.SRL || io.isa.SRLI || io.isa.SRLW || io.isa.SRLIW || io.isa.SRA || io.isa.SRAI || io.isa.SRAW || io.isa.SRAIW
203-
protected val comp = io.isa.SLT || io.isa.SLTI || io.isa.SLTU || io.isa.SLTIU
204-
protected val link = io.isa.JAL || io.isa.JALR
205-
protected val branch = io.isa.BEQ || io.isa.BNE || io.isa.BLT || io.isa.BGE || io.isa.BLTU || io.isa.BGEU
206-
protected val load = io.isa.LD || io.isa.LW || io.isa.LH || io.isa.LB || io.isa.LWU || io.isa.LHU || io.isa.LBU
207-
protected val store = io.isa.SD || io.isa.SW || io.isa.SH || io.isa.SB
208-
protected val sync = io.isa.FENCE || io.isa.FENCE_I
209-
protected val env = io.isa.ECALL || io.isa.EBREAK
210-
protected val csr = io.isa.CSRRW || io.isa.CSRRS || io.isa.CSRRC || io.isa.CSRRWI || io.isa.CSRRSI || io.isa.CSRRCI
211-
protected val priv = io.isa.MRET || io.isa.SRET || io.isa.WFI || io.isa.SFENCE_VMA
212-
protected val custom = io.isa.GCD
199+
protected val csr = io.isa.CSRRW || io.isa.CSRRS || io.isa.CSRRC || io.isa.CSRRWI || io.isa.CSRRSI || io.isa.CSRRCI
213200

214201
protected val decodeTable = Array(
215202
// i type inst
216-
ISADecoder.ADDI -> List(iInstType),
217-
ISADecoder.ADDIW -> List(iInstType),
218-
ISADecoder.SLTI -> List(iInstType),
219-
ISADecoder.SLTIU -> List(iInstType),
220-
ISADecoder.ANDI -> List(iInstType),
221-
ISADecoder.ORI -> List(iInstType),
222-
ISADecoder.XORI -> List(iInstType),
223-
ISADecoder.SLLI -> List(iInstType),
224-
ISADecoder.SLLIW -> List(iInstType),
225-
ISADecoder.SRLI -> List(iInstType),
226-
ISADecoder.SRLIW -> List(iInstType),
227-
ISADecoder.SRAI -> List(iInstType),
228-
ISADecoder.SRAIW -> List(iInstType),
203+
ISADecoder.ADDI -> List(iInstType, wtRegTrue),
204+
ISADecoder.ADDIW -> List(iInstType, wtRegTrue),
205+
ISADecoder.SLTI -> List(iInstType, wtRegTrue),
206+
ISADecoder.SLTIU -> List(iInstType, wtRegTrue),
207+
ISADecoder.ANDI -> List(iInstType, wtRegTrue),
208+
ISADecoder.ORI -> List(iInstType, wtRegTrue),
209+
ISADecoder.XORI -> List(iInstType, wtRegTrue),
210+
ISADecoder.SLLI -> List(iInstType, wtRegTrue),
211+
ISADecoder.SLLIW -> List(iInstType, wtRegTrue),
212+
ISADecoder.SRLI -> List(iInstType, wtRegTrue),
213+
ISADecoder.SRLIW -> List(iInstType, wtRegTrue),
214+
ISADecoder.SRAI -> List(iInstType, wtRegTrue),
215+
ISADecoder.SRAIW -> List(iInstType, wtRegTrue),
229216
// u type inst
230-
ISADecoder.LUI -> List(uInstType),
231-
ISADecoder.AUIPC -> List(uInstType),
217+
ISADecoder.LUI -> List(uInstType, wtRegTrue),
218+
ISADecoder.AUIPC -> List(uInstType, wtRegTrue),
232219
// r type inst
233-
ISADecoder.ADD -> List(rInstType),
234-
ISADecoder.ADDW -> List(rInstType),
235-
ISADecoder.SLT -> List(rInstType),
236-
ISADecoder.SLTU -> List(rInstType),
237-
ISADecoder.AND -> List(rInstType),
238-
ISADecoder.OR -> List(rInstType),
239-
ISADecoder.XOR -> List(rInstType),
240-
ISADecoder.SLL -> List(rInstType),
241-
ISADecoder.SLLW -> List(rInstType),
242-
ISADecoder.SRL -> List(rInstType),
243-
ISADecoder.SRLW -> List(rInstType),
244-
ISADecoder.SUB -> List(rInstType),
245-
ISADecoder.SUBW -> List(rInstType),
246-
ISADecoder.SRA -> List(rInstType),
247-
ISADecoder.SRAW -> List(rInstType),
220+
ISADecoder.ADD -> List(rInstType, wtRegTrue),
221+
ISADecoder.ADDW -> List(rInstType, wtRegTrue),
222+
ISADecoder.SLT -> List(rInstType, wtRegTrue),
223+
ISADecoder.SLTU -> List(rInstType, wtRegTrue),
224+
ISADecoder.AND -> List(rInstType, wtRegTrue),
225+
ISADecoder.OR -> List(rInstType, wtRegTrue),
226+
ISADecoder.XOR -> List(rInstType, wtRegTrue),
227+
ISADecoder.SLL -> List(rInstType, wtRegTrue),
228+
ISADecoder.SLLW -> List(rInstType, wtRegTrue),
229+
ISADecoder.SRL -> List(rInstType, wtRegTrue),
230+
ISADecoder.SRLW -> List(rInstType, wtRegTrue),
231+
ISADecoder.SUB -> List(rInstType, wtRegTrue),
232+
ISADecoder.SUBW -> List(rInstType, wtRegTrue),
233+
ISADecoder.SRA -> List(rInstType, wtRegTrue),
234+
ISADecoder.SRAW -> List(rInstType, wtRegTrue),
248235
// nop inst
249-
ISADecoder.NOP -> List(nopInstType),
236+
ISADecoder.NOP -> List(nopInstType, wtRegFalse),
250237
// j type inst
251-
ISADecoder.JAL -> List(jInstType),
252-
ISADecoder.JALR -> List(iInstType),
238+
ISADecoder.JAL -> List(jInstType, wtRegTrue),
239+
ISADecoder.JALR -> List(iInstType, wtRegTrue),
253240
// b type inst
254-
ISADecoder.BEQ -> List(bInstType),
255-
ISADecoder.BNE -> List(bInstType),
256-
ISADecoder.BLT -> List(bInstType),
257-
ISADecoder.BLTU -> List(bInstType),
258-
ISADecoder.BGE -> List(bInstType),
259-
ISADecoder.BGEU -> List(bInstType),
241+
ISADecoder.BEQ -> List(bInstType, wtRegFalse),
242+
ISADecoder.BNE -> List(bInstType, wtRegFalse),
243+
ISADecoder.BLT -> List(bInstType, wtRegFalse),
244+
ISADecoder.BLTU -> List(bInstType, wtRegFalse),
245+
ISADecoder.BGE -> List(bInstType, wtRegFalse),
246+
ISADecoder.BGEU -> List(bInstType, wtRegFalse),
260247
// special i type inst
261-
ISADecoder.LB -> List(iInstType),
262-
ISADecoder.LBU -> List(iInstType),
263-
ISADecoder.LH -> List(iInstType),
264-
ISADecoder.LHU -> List(iInstType),
265-
ISADecoder.LW -> List(iInstType),
266-
ISADecoder.LWU -> List(iInstType),
267-
ISADecoder.LD -> List(iInstType),
248+
ISADecoder.LB -> List(iInstType, wtRegTrue),
249+
ISADecoder.LBU -> List(iInstType, wtRegTrue),
250+
ISADecoder.LH -> List(iInstType, wtRegTrue),
251+
ISADecoder.LHU -> List(iInstType, wtRegTrue),
252+
ISADecoder.LW -> List(iInstType, wtRegTrue),
253+
ISADecoder.LWU -> List(iInstType, wtRegTrue),
254+
ISADecoder.LD -> List(iInstType, wtRegTrue),
268255
// s type inst
269-
ISADecoder.SB -> List(sInstType),
270-
ISADecoder.SH -> List(sInstType),
271-
ISADecoder.SW -> List(sInstType),
272-
ISADecoder.SD -> List(sInstType),
256+
ISADecoder.SB -> List(sInstType, wtRegFalse),
257+
ISADecoder.SH -> List(sInstType, wtRegFalse),
258+
ISADecoder.SW -> List(sInstType, wtRegFalse),
259+
ISADecoder.SD -> List(sInstType, wtRegFalse),
273260
// csr inst
274-
ISADecoder.CSRRW -> List(iInstType),
275-
ISADecoder.CSRRS -> List(iInstType),
276-
ISADecoder.CSRRC -> List(iInstType),
277-
ISADecoder.CSRRWI -> List(iInstType),
278-
ISADecoder.CSRRSI -> List(iInstType),
279-
ISADecoder.CSRRCI -> List(iInstType),
261+
ISADecoder.CSRRW -> List(iInstType, wtRegTrue),
262+
ISADecoder.CSRRS -> List(iInstType, wtRegTrue),
263+
ISADecoder.CSRRC -> List(iInstType, wtRegTrue),
264+
ISADecoder.CSRRWI -> List(iInstType, wtRegTrue),
265+
ISADecoder.CSRRSI -> List(iInstType, wtRegTrue),
266+
ISADecoder.CSRRCI -> List(iInstType, wtRegTrue),
280267
// system inst
281-
ISADecoder.ECALL -> List(nopInstType),
282-
ISADecoder.MRET -> List(nopInstType),
283-
ISADecoder.FENCE -> List(nopInstType),
284-
ISADecoder.FENCE_I -> List(nopInstType),
268+
ISADecoder.ECALL -> List(nopInstType, wtRegFalse),
269+
ISADecoder.MRET -> List(nopInstType, wtRegFalse),
270+
ISADecoder.FENCE -> List(nopInstType, wtRegFalse),
271+
ISADecoder.FENCE_I -> List(nopInstType, wtRegFalse),
285272
// custom inst
286-
ISADecoder.CUST -> List(nopInstType)
273+
ISADecoder.CUST -> List(nopInstType, wtRegFalse)
287274
)
288275

289276
protected val immExten = Module(new ImmExten)
290-
protected val defRes = List(nopInstType)
291-
277+
protected val defRes = List(nopInstType, wtRegFalse)
278+
protected val decRes = ListLookup(io.inst, defRes, decodeTable)
292279
immExten.io.inst := io.inst
293-
immExten.io.instType := ListLookup(io.inst, defRes, decodeTable)(0)
280+
immExten.io.instType := decRes(0)
294281
io.imm := immExten.io.imm
295282
io.csr := csr
296-
io.wen := arith || logc || shift || comp || link || load || csr || custom
283+
io.wen := decRes(1) // NOTE: the csr inst type
297284
}

‎rtl/tc_l2/src/main/scala/port/ISAIO.scala‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -80,5 +80,4 @@ class ISAIO extends Bundle {
8080
val REMU = Bool()
8181
val REMUW = Bool()
8282
val REMW = Bool()
83-
val GCD = Bool()
8483
}

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