feat: add inst and axi4 config trait

Author: maksyuki

rtl/tc_l3/src/main/scala/common/AXI4Config.scala

@@ -0,0 +1,18 @@
+package treecorel2
+
+import chisel3._
+import chisel3.util._
+
+trait AXI4Config extends IOConfig {
+  val AxiProtLen   = 3
+  val AxiIdLen     = 4
+  val AxiUserLen   = 1
+  val AxiSizeLen   = 3
+  val AxiLen       = 8
+  val AxiStrb      = 8
+  val AxiBurstLen  = 2
+  val AxiCacheLen  = 4
+  val AxiQosLen    = 4
+  val AxiRegionLen = 4
+  val AxiRespLen   = 2
+}

rtl/tc_l3/src/main/scala/common/InstConfig.scala

@@ -0,0 +1,39 @@
+package treecorel2
+
+import chisel3._
+import chisel3.util._
+
+trait IOConfig {
+  val XLen       = 64
+  val InstLen    = 32
+  val RegfileLen = 5
+  val RegfileNum = 1 << RegfileLen
+  val ISALen     = 6
+  // branch prediction
+  val GHRLen    = 5
+  val PHTSize   = 1 << GHRLen
+  val BTBIdxLen = 5
+  val BTBPcLen  = XLen - BTBIdxLen
+  val BTBTgtLen = XLen
+  val BTBSize   = 1 << BTBIdxLen
+}
+
+trait InstConfig extends IOConfig {
+  val SoCEna   = true
+  val CacheEna = false
+
+  // cache
+  val NWay          = 4
+  val NBank         = 4
+  val NSet          = 32
+  val CacheLineSize = XLen * NBank
+  val ICacheSize    = NWay * NSet * CacheLineSize
+  val DCacheSize    = NWay * NSet * CacheLineSize
+
+  // clint
+  val ClintBaseAddr  = 0x02000000.U(XLen.W)
+  val ClintBoundAddr = 0x0200bfff.U(XLen.W)
+  val MSipOffset     = 0x0.U(XLen.W)
+  val MTimeOffset    = 0xbff8.U(XLen.W)
+  val MTimeCmpOffset = 0x4000.U(XLen.W)
+}