You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
<p align="center">A RISC-V soft core processor written from scratch.</p>
3
+
<h1 align="center">TreeCore CPU</h1>
4
+
<p align="center">A series of RISC-V soft core processor written from scratch</p>
5
5
</p>
6
6
<palign="center">
7
7
<a href="./LICENSE">
@@ -18,27 +18,47 @@
18
18
<a href="./README_zh-CN.md">简体中文</a>
19
19
</p>
20
20
21
-
## Preface
21
+
## Overview
22
+
the TreeCore L2 is the
22
23
23
-
I heard the word RISC-V for the first time in the second semester of my junior year (that is, the summer of 2016), my roommate happened to participate in the pilot class of "Computer Architecture" organized by the college, and **their task was to design a simple soft-core CPU based on the RISC-V instruction set**. At that time, I only knew that it was an open source RISC instruction set launched by the University of Berkeley, I felt that it was similar to the MIPS instruction set used in our ordinary classes, so I didn't take it too seriously. But what is unexpected is that after just a few years of development, the RISC-V instruction set has been supported by many Internet and semiconductor giants around the world, and more and more research institutions and start-ups begin to design their own proprietary processors based on it. I think the current RISC-V is just like the early Linux kernel, although the function and performance are still very limited, with the power of open source collaboration, **I believe RISC-V will one day usher in a revolution that can change the old pattern in some areas**. Therefore, in order not to be abandoned by the coming new era, as an amateur hardware enthusiast, I think it is necessary for me to learn the RISC-V instruction set, maybe I will have the opportunity to contribute to the design and R & D of domestic independent controllable processor in the future!
24
+
## Feature
25
+
* 64-bit five-stage pipeline RISC-V ISA CPU core.
26
+
* support RISC-V integer(I) instruction set.
27
+
* supports machine mode privilege levels.
28
+
* supports AXI4 inst and mem acess.
29
+
* can boot rt-thread.
24
30
25
-
The ancients once said: **it’s always shallow on paper, and you must do it yourself**, since you decide to learn RISC-V, you must practice it to understand it. For this kind of project at the bottom of computer architecture, there is no better way than to realize it from scratch. So with this idea, I started to collect information on the Internet, and the results were disappointing. Although there are many foreign open source projects related to RISC-V, many of them are implemented using Chisel, a high-level hardware construction language. The learning threshold is very high. In addition, in order to pursue the overall performance, some CPU system architectures are designed to be very complex (such as using five-level or more pipelines, multi-core processing, out-of-order execution, etc), it is very difficult for beginners to get started. So after careful consideration, I decided to write an open source processor project from scratch, which has a **simple system architecture, clear code and excellent package**, I hope it can be like Arduino, which stands out from many microcontrollers, so that more hardware enthusiasts can quickly start to experience, and develop many interesting applications based on it. In the future, under the mutual promotion of the software and hardware ecological environment, maybe more people will like CPU development and be willing to spend time on it. If I can really do this, I will be satisfied.
-4. change the sim memory from 8G to 256MB. need to enter 'make menuconfig' and modify [Memory - Configuration]->[Memory size] to '0x10000000' manually
change the sim memory from 8G to 256MB. need to enter 'make menuconfig' and modify [Memory - Configuration]->[Memory size] to '0x10000000' manually.
55
+
cd in root rtl dir
56
+
```bash
57
+
$ make nemuBuild
58
+
$ make diffBuild
59
+
$ make difftestBuild
60
+
$ make demoTest
61
+
```
42
62
43
63
### Software test
44
64
@@ -54,9 +74,16 @@ The ancients once said: **it’s always shallow on paper, and you must do it you
54
74
55
75
## Summary
56
76
77
+
## Documention
78
+
57
79
## Plan
58
80
59
81
## Update
60
82
61
-
## Copyright
83
+
## License
84
+
85
+
## Story
62
86
87
+
I heard the word RISC-V for the first time in the second semester of my junior year (that is, the summer of 2016), my roommate happened to participate in the pilot class of "Computer Architecture" organized by the college, and **their task was to design a simple soft-core CPU based on the RISC-V instruction set**. At that time, I only knew that it was an open source RISC instruction set launched by the University of Berkeley, I felt that it was similar to the MIPS instruction set used in our ordinary classes, so I didn't take it too seriously. But what is unexpected is that after just a few years of development, the RISC-V instruction set has been supported by many Internet and semiconductor giants around the world, and more and more research institutions and start-ups begin to design their own proprietary processors based on it. I think the current RISC-V is just like the early Linux kernel, although the function and performance are still very limited, with the power of open source collaboration, **I believe RISC-V will one day usher in a revolution that can change the old pattern in some areas**. Therefore, in order not to be abandoned by the coming new era, as an amateur hardware enthusiast, I think it is necessary for me to learn the RISC-V instruction set, maybe I will have the opportunity to contribute to the design and R & D of domestic independent controllable processor in the future!
88
+
89
+
The ancients once said: **it’s always shallow on paper, and you must do it yourself**, since you decide to learn RISC-V, you must practice it to understand it. For this kind of project at the bottom of computer architecture, there is no better way than to realize it from scratch. So with this idea, I started to collect information on the Internet, and the results were disappointing. Although there are many foreign open source projects related to RISC-V, many of them are implemented using Chisel, a high-level hardware construction language. The learning threshold is very high. In addition, in order to pursue the overall performance, some CPU system architectures are designed to be very complex (such as using five-level or more pipelines, multi-core processing, out-of-order execution, etc), it is very difficult for beginners to get started. So after careful consideration, I decided to write an open source processor project from scratch, which has a **simple system architecture, clear code and excellent package**, I hope it can be like Arduino, which stands out from many microcontrollers, so that more hardware enthusiasts can quickly start to experience, and develop many interesting applications based on it. In the future, under the mutual promotion of the software and hardware ecological environment, maybe more people will like CPU development and be willing to spend time on it. If I can really do this, I will be satisfied.
0 commit comments