reduce pressure on CPU register #737
                
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Wanted to do more but this patch is simple.
On none AVX512 CPU there is only 16 register. The compiler do not reorder the madd ops on sgemm, so did chose op order on build time.
pp have +20/50% CPU with only 16 AVX2 register, for bf16 and fp16 quantisation.
with curent 0.9.2 release:
with this patch:
and even best with FP16:
with curent 0.9.2 release:
with this patch:
Note: LocalScore is realy nice. 👍