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@muditbhargava66 muditbhargava66 released this 08 Jan 18:37
· 4 commits to main since this release
v1.4.0
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Cache Simulator v1.4.0

Release Date: 2026-01-08

Highlights

This release introduces L3 cache support, extended coherence protocols (MSI/MOESI), new interconnect topologies (Ring/Torus), and significant code quality improvements through modularization.

New Features

L3 Cache Support

  • Optional third cache level in MemoryHierarchy with inclusive policy
  • Configurable via JSON configuration with l3 section
  • Full statistics support: getL3Misses(), getL3HitRate(), getL3MissRate()
  • Proper inclusive cache behavior for multi-core coherence

Extended Coherence Protocols

  • MSI Protocol: 3-state coherence (Modified, Shared, Invalid)
  • MOESI Protocol: 5-state coherence (Modified, Owned, Exclusive, Shared, Invalid)
  • Abstract CoherenceProtocolBase interface with factory pattern
  • MOESI Owned state enables dirty sharing without memory writeback
  • State transition tracking and comprehensive statistics

New Interconnect Topologies

  • Ring Interconnect: Bidirectional ring with shortest path routing
    • Latency: min(clockwise, counterclockwise) * hopLatency
  • Torus Interconnect: 2D torus with wrap-around connections
    • Latency: (wrapDx + wrapDy) * hopLatency
  • Full implementation of InterconnectInterface

Modular Code Organization

  • CLI Parser Module: Extracted command-line parsing to utils/cli_parser.h/cpp
  • Cache Visualization Module: Extracted cache state visualization to utils/cache_visualization.h/cpp
  • Refactored main.cpp from 822 to 442 lines (-46%)

Multiprocessor Configuration

  • Added coherenceProtocol selection: MSI, MESI, MOESI
  • Added interconnectType selection: Bus, Crossbar, Mesh, Ring, Torus
  • Configuration via MultiProcessorSystem::Config struct

Documentation

  • Added docs/features/l3-cache.md
  • Added docs/features/coherence-protocols.md
  • Added docs/features/interconnects.md
  • Updated docs/README.md with new feature links
  • Updated user/configuration.md with L3 and protocol options

Testing

  • 4 new unit test files added
  • All 18 tests passing (100%)
  • Test coverage for:
    • MSI/MOESI protocol state transitions
    • L3 cache access patterns
    • Ring/Torus interconnect routing
    • CLI parsing functionality

Installation

git clone https://github.com/muditbhargava66/CacheSimulator.git
cd CacheSimulator
mkdir build && cd build
cmake -DCMAKE_BUILD_TYPE=Release ..
cmake --build . --parallel

Requirements

  • C++20 compatible compiler (GCC 10+, Clang 10+, MSVC 2019+)
  • CMake 3.14+

Full Changelog

See CHANGELOG.md for complete details.

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