pl35x-nand-controller: Enable dynamically setting clk rate in NAND.#210
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nit: I don't think tab/spacing in commit description is required.
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Your PR description only mentions testing for "happy path".
Did you also test all the possible failure paths in this code?
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Yes I did. Updated the PR description with all the test cases and their outcomes. |
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NI Zynq based devices require different clk frequencies to be set at different timing modes. Enable the memclk rate to be set according to the specifications in the device tree. If the device tree does not have this memclk-timing-frequency property specified, the driver proceeds as usual. Signed-off-by: deooi <deborah.ooi@ni.com>
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NI Zynq based devices require different nand memclk frequencies to be set at different timing modes, as seen in the bluefin branch of ni-zynq.dtsi.
This commit enables the memclk rate to be set according to the specifications in the device tree. If the device tree does not have this memclk-timing-frequency property specified, the driver proceeds as usual.
WI: AB#3024184
Testing:
Tested my changes on cDAQ9189, NAND timing mode was able to be set successfully and NAND device was detected.
Tested with memclk-timing-frequency property not set in device tree and we get the error as expected. This printk error message is not part of the commit, just there for my own checking. Purposely not including it in the commit as it is not actually an error if the device does not have that property.
Tested with passing a non-existent timing mode (99) into the timing mode parameter of of_get_memclk_freq. Got the expected error.
