A complete, reproducible workflow for detecting and filtering noise from a voice audio signal. Uses MATLAB for signal analysis, frequency characterization, filter design, and audio/binary conversion. Implements and simulates the digital filter in Verilog with a full hardware datapath and FSM controller. The result is a practical system that processes and reconstructs real audio through a true hardware-accurate pipeline.
📦 Source code and images available at:
GitHub Repository
- Overview
- Features
- Prerequisites
- Block Diagram
- State Machine Diagram
- How It Works
- Project Structure
- Project Structure (Without Controller)
- Example Workflow
- Usage Instructions
- Sample Result
- Credits
This project demonstrates a practical signal-processing pipeline:
- FFT-based noise detection and visualization
- Chebyshev Type II IIR filter design
- Fixed-point coefficient conversion (Q6.57 format: 1 sign bit + 6 integer bits + 57 fractional bits)
- Audio format conversion (Q0.15 format: 1 sign bit + 15 fractional bits) for hardware simulation
- Hardware-accurate Verilog datapath and FSM controller
- End-to-end simulation with testbench and audio reconstruction
- MATLAB scripts for full signal inspection, filter synthesis, and file I/O
- Highly modular Verilog design: includes datapath, controller, register, ROM, and clipper modules
- Automated fixed-point scaling for both coefficient and audio data
- File-based Verilog testbench; no manual stimulus required
- Includes block diagrams and FSM charts for pipeline and control logic visualization
- MATLAB R2020b or newer
- Verilog simulation tool (e.g., ModelSim or Vivado Simulator)
- Audio file in mono 16-bit PCM format (
input.wav
)
System datapath architecture (Verilog implementation with controller):
Controller finite-state machine (FSM) for filter sequencing:
- Use
noise_detection.m
to load your audio file and plot the FFT of both the "noise-only" segment and the full audio. - Identify the main noise frequency and compare it against the total signal.
*FFT of full signal: speech energy mostly at lower frequencies; noise spike still visible
- Determine target filter characteristics based on plots—e.g., set a low-pass cutoff just below the noise frequency.
- Run
Coeffcient_Extraction_And_Test.m
:- The filter is synthesized using a Chebyshev Type II low-pass design, tailored to suppress the detected noise frequency (~1500 Hz).
- Coefficients are scaled and formatted (Q6.57) for Verilog ROM.
audio_To_Q0.15_Binary.m
: converts WAV samples to 16-bit Q0.15 binary (for testbench input).
- Datapath: Implements Direct Form I/II MAC structure, using pipelined shift registers, accumulator, and ROM coefficient lookup.
- Controller: FSM (see diagram above) synchronizes sampling, loading, and accumulation cycles.
- ROM: Stores the fixed-point coefficients used at each filter tap.
- Testbench (
Digital_Filter_TB.v
): Reads binary samples, feeds them to the filter, writes output tooutput_samples.txt
.
q0.15_Binary_To_Audio.m
: converts the binary stream of filtered samples back to a floating-point WAV (output.wav
) for audible quality verification.
File/Folder | Description |
---|---|
noise_detection.m |
FFT analysis and noise visualization in MATLAB |
Coeffcient_Extraction_And_Test.m |
Filter coefficient extraction + export (Q6.57) + test that your filter works |
audio_To_Q0.15_Binary.m |
Convert WAV audio to Q0.15 binary samples for simulation |
q0.15_Binary_To_Audio.m |
Reconverts filtered binary output into WAV |
Digital_Filter_TopModule.v |
Top-level Verilog digital filter (controller + datapath) |
Controller.v |
FSM for datapath sequencing |
Data_Path.v |
Core multiply-accumulate datapath module |
Coeffs_ROM.v |
Fixed-point coefficient ROM for the digital filter |
Register.v |
Parameterized synchronous/asynchronous register module |
Counter.v |
Cycle counter for filter taps |
Clipper.v |
Q7.64 saturating to Q0.63 output |
Digital_Filter_TB.v |
Testbench for batch input and output |
This version implements the filter using a synchronous datapath without an explicit FSM controller, relying on always blocks and generate statements for multiplication and summation.
File/Folder | Description |
---|---|
noise_detection.m |
FFT analysis and noise visualization in MATLAB |
Coeffcient_Extraction_And_Test.m |
Filter coefficient extraction, export (Q6.57), and filter testing |
audio_To_Q0.15_Binary.m |
Convert WAV audio to Q0.15 binary samples for simulation |
q0.15_Binary_To_Audio.m |
Reconverts filtered binary output into WAV |
Data_Path.v |
Core multiply-accumulate datapath module (without controller) |
Clipper.v |
Q7.64 saturating to Q0.63 output |
Tb.v |
Testbench for batch input and output |
-
Analyze spectra:
noise_detection.m
→ Plots noise & total signal FFT to guide filter design. -
Design filter:
Coeffcient_Extraction_And_Test.m
→ Designs & exports Q6.57 coefficients. -
Convert audio for hardware:
audio_To_Q0.15_Binary.m
→ Input WAV to binary samples. -
Simulate in Verilog:
Load all.v
files + ROM in simulator.
RunDigital_Filter_TB.v
(orTb.v
for without controller) → Binary output produced. -
Convert back to audio:
q0.15_Binary_To_Audio.m
→ Final output WAV for quality check.
- Place your input WAV as
input.wav
. - Run
noise_detection.m
to inspect noise and speech spectra. - Run
Coeffcient_Extraction_And_Test.m
for filter design/export. - Use
audio_To_Q0.15_Binary.m
to generateinput_samples.txt
.
- Add all source modules and
Digital_Filter_TB.v
(orTb.v
for without controller) to your simulator. - Ensure
input_samples.txt
is present in the simulation working directory. - Run simulation: output is saved as
output_samples.txt
.
- Use
q0.15_Binary_To_Audio.m
to get your finaloutput.wav
. - Listen and compare to verify noise attenuation and speech preservation.
After filtering, the background noise (~1500Hz tone) was successfully attenuated while preserving speech clarity.
Listen to the filtered result: output.wav
Developed by [Nima].
MATLAB and Verilog sources provided for educational and research purposes.
Questions or suggestions? Please open an issue or contribute!
Enjoy a clean signal from algorithm to hardware!