Minor module updates

Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>

Author: npmitche

chipsec/hal/intel/mmcfg.py

@@ -154,9 +154,8 @@ def read_mmcfg_reg(self, bus: int, dev: int, fun: int, off: int, size: int) -> i
         pciexbar, pciexbar_sz = self.get_MMCFG_base_address(bus)
         pciexbar_off = (bus * 32 * 8 + dev * 8 + fun) * 0x1000 + off
         value = self.cs.hals.MMIO.read_MMIO_reg(pciexbar, pciexbar_off, size, pciexbar_sz)
-        self.logger.log_hal(f"[mmcfg] Reading MMCFG register at bus {bus}, device {dev}, function {fun}, offset 0x{off:X}")
-        self.logger.log_hal("[mmcfg] reading {:02d}:{:02d}.{:d} + 0x{:02X} (MMCFG + 0x{:08X}): 0x{:08X}".format(
-            bus, dev, fun, off, pciexbar_off, value))
+        self.logger.log_hal(f"[mmcfg] Reading MMCFG register at bus 0x{bus:X}, device 0x{dev:X}, function 0x{fun:X}, offset 0x{off:X}")
+        self.logger.log_hal(f"[mmcfg]     (MMCFG + 0x{pciexbar_off:08X}): 0x{value:08X}")
         if 1 == size:
             return (value & 0xFF)
         elif 2 == size:
@@ -183,9 +182,8 @@ def write_mmcfg_reg(self, bus: int, dev: int, fun: int, off: int, size: int, val
         else:
             mask = 0xFFFFFFFF
         self.cs.hals.MMIO.write_MMIO_reg(pciexbar, pciexbar_off, (value & mask), size)
-        self.logger.log_hal(f"[mmcfg] Writing value 0x{value:X} to MMCFG register at bus {bus}, device {dev}, function {fun}, offset 0x{off:X}")
-        self.logger.log_hal("[mmcfg] writing {:02d}:{:02d}.{:d} + 0x{:02X} (MMCFG + 0x{:08X}): 0x{:08X}".format(
-            bus, dev, fun, off, pciexbar_off, value))
+        self.logger.log_hal(f"[mmcfg] Writing value 0x{value:X} to MMCFG register at bus 0x{bus:X}, device 0x{dev:X}, function 0x{fun:X}, offset 0x{off:X}")
+        self.logger.log_hal(f"[mmcfg]     (MMCFG + 0x{pciexbar_off:08X}): 0x{value:08X}")
         return True
 
     def get_extended_capabilities(self, bus: int, dev: int, fun: int) -> List[ECEntry]:
@@ -207,7 +205,7 @@ def get_extended_capabilities(self, bus: int, dev: int, fun: int) -> List[ECEntr
                 self.logger.log_hal(f"[mmcfg] Error reading extended capability at offset 0x{off:X}: {e}")
                 break
         if not retcap:
-            self.logger.log_hal(f"[mmcfg] No extended capabilities found for {bus}:{dev}.{fun}")
+            self.logger.log_hal(f"[mmcfg] No extended capabilities found for {bus:X}:{dev:X}.{fun:X}")
         return retcap
 
     def get_vsec(self, bus: int, dev: int, fun: int, ecoff: int) -> VSECEntry:

chipsec/modules/common/me_mfg_mode.py

@@ -122,15 +122,20 @@ def is_supported(self) -> bool:
 
     def check_me_mfg_mode(self) -> int:
         me_mfg_mode_res = ModuleResult.FAILED
-        me_hfs_reg = self.cs.register.get_list_by_name('HFS')
+        me_hfs_reg = self.cs.register.get_list_by_name('HFS').filter_with_field('MFG_MODE')
         me_hfs_reg.read_and_verbose_print()
 
-        if me_hfs_reg.is_all_field_value(0, 'MFG_MODE'):
-            me_mfg_mode_res = ModuleResult.PASSED
-            self.logger.log_passed('ME is not in Manufacturing Mode')
+        if me_hfs_reg:
+            if me_hfs_reg.is_all_field_value(0, 'MFG_MODE'):
+                me_mfg_mode_res = ModuleResult.PASSED
+                self.logger.log_passed('ME is not in Manufacturing Mode')
+            else:
+                self.logger.log_failed('ME is in Manufacturing Mode')
+                self.result.setStatusBit(self.result.status.POTENTIALLY_VULNERABLE)
         else:
-            self.logger.log_failed('ME is in Manufacturing Mode')
-            self.result.setStatusBit(self.result.status.POTENTIALLY_VULNERABLE)
+            self.logger.log_warning('ME HFS register cannot be found.')
+            self.result.setStatusBit(self.result.status.REGISTER_NOT_DEFINED)
+            me_mfg_mode_res = ModuleResult.WARNING
 
         return self.result.getReturnCode(me_mfg_mode_res)