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mstasiaknordicrlubos
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boards: nordic: nrf54lm20pdk: introduce renamed nrf54lm20pdk board
Introduced board nrf54lm20pdk, identical to nrf54lm20apdk. Signed-off-by: Michał Stasiak <[email protected]>
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‎boards/nordic/nrf54lm20pdk/Kconfig.defconfig‎

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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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if BOARD_NRF54LM20PDK_NRF54LM20A_CPUAPP
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config ROM_START_OFFSET
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default 0 if PARTITION_MANAGER_ENABLED
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default 0x800 if BOOTLOADER_MCUBOOT
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config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE
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default y
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endif # BOARD_NRF54LM20PDK_NRF54LM20A_CPUAPP

‎boards/nordic/nrf54lm20pdk/Kconfig.nrf54lm20pdk‎

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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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config BOARD_NRF54LM20PDK
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select SOC_NRF54LM20A_ENGA_CPUAPP if BOARD_NRF54LM20PDK_NRF54LM20A_CPUAPP

‎boards/nordic/nrf54lm20pdk/board.cmake‎

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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
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include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

‎boards/nordic/nrf54lm20pdk/board.yml‎

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board:
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name: nrf54lm20pdk
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full_name: nRF54LM20 PDK
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vendor: nordic
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socs:
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- name: nrf54lm20a
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revision:
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format: custom
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default: "0.0.0"
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revisions:
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- name: "0.0.0"
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- name: "0.2.0"
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- name: "0.2.0.csp"

‎boards/nordic/nrf54lm20pdk/nrf54lm20a_cpuapp_common.dtsi‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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/* This file is common to the secure and non-secure domain */
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#include <nordic/nrf54lm20a_enga_cpuapp.dtsi>
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#include "nrf54lm20pdk_nrf54lm20a-common.dtsi"
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/ {
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chosen {
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zephyr,console = &uart20;
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zephyr,shell-uart = &uart20;
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zephyr,uart-mcumgr = &uart20;
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zephyr,bt-mon-uart = &uart20;
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zephyr,bt-c2h-uart = &uart20;
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zephyr,flash-controller = &rram_controller;
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zephyr,flash = &cpuapp_rram;
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zephyr,bt-hci = &bt_hci_controller;
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zephyr,ieee802154 = &ieee802154;
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};
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};
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&cpuapp_sram {
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status = "okay";
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};
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&hfpll {
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/* For now use 64 MHz clock for CPU and fast peripherals. */
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clock-frequency = <DT_FREQ_M(64)>;
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};
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&lfxo {
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load-capacitors = "internal";
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load-capacitance-femtofarad = <15500>;
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};
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&hfxo {
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load-capacitors = "internal";
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load-capacitance-femtofarad = <15000>;
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};
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&grtc {
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owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
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/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
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child-owned-channels = <3 4 7 8 9 10 11>;
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status = "okay";
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};
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&cpuapp_rram {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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slot0_partition: partition@10000 {
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label = "image-0";
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reg = <0x10000 DT_SIZE_K(449)>;
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};
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slot0_ns_partition: partition@80400 {
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label = "image-0-nonsecure";
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reg = <0x80400 DT_SIZE_K(449)>;
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};
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slot1_partition: partition@f0800 {
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label = "image-1";
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reg = <0xf0800 DT_SIZE_K(449)>;
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};
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slot1_ns_partition: partition@160c00 {
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label = "image-1-nonsecure";
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reg = <0x160c00 DT_SIZE_K(449)>;
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};
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storage_partition: partition@1d1000 {
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label = "storage";
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reg = <0x1d1000 DT_SIZE_K(36)>;
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};
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};
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};
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&uart20 {
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status = "okay";
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpiote20 {
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status = "okay";
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};
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&gpiote30 {
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status = "okay";
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};
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&radio {
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status = "okay";
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};
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&temp {
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status = "okay";
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};
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&clock {
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status = "okay";
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};
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&bt_hci_controller {
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status = "okay";
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};
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&ieee802154 {
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status = "okay";
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};
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zephyr_udc0: &usbhs {
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status = "okay";
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};
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&spi00 {
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status = "okay";
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cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&spi00_default>;
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pinctrl-1 = <&spi00_sleep>;
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pinctrl-names = "default", "sleep";
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mx25r64: mx25r6435f@0 {
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compatible = "jedec,spi-nor";
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status = "okay";
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reg = <0>;
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spi-max-frequency = <8000000>;
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jedec-id = [c2 28 17];
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sfdp-bfp = [
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e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb
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ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
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10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44
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30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
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];
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size = <67108864>;
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has-dpd;
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t-enter-dpd = <10000>;
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t-exit-dpd = <35000>;
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};
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};

‎boards/nordic/nrf54lm20pdk/nrf54lm20pdk_nrf54lm20a-common.dtsi‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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#include "nrf54lm20pdk_nrf54lm20a-pinctrl.dtsi"
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/ {
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leds {
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compatible = "gpio-leds";
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led0: led_0 {
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gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
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label = "Green LED 0";
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};
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led1: led_1 {
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gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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label = "Green LED 1";
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};
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led2: led_2 {
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gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
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label = "Green LED 2";
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};
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led3: led_3 {
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gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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label = "Green LED 3";
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};
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};
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pwmleds {
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compatible = "pwm-leds";
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/*
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* PWM signal can be exposed on GPIO pin only within same domain.
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* There is only one domain which contains both PWM and GPIO:
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* PWM20/21/22 and GPIO Port P1/P3.
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* Only LEDs connected to P1/P3 can work with PWM, for example LED1.
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*/
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pwm_led1: pwm_led_1 {
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pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
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};
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};
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buttons {
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compatible = "gpio-keys";
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button0: button_0 {
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gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 0";
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zephyr,code = <INPUT_KEY_0>;
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};
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button1: button_1 {
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gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 1";
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zephyr,code = <INPUT_KEY_1>;
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};
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button2: button_2 {
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gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 2";
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zephyr,code = <INPUT_KEY_2>;
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};
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button3: button_3 {
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gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 3";
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zephyr,code = <INPUT_KEY_3>;
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};
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};
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aliases {
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led0 = &led0;
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led1 = &led1;
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led2 = &led2;
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led3 = &led3;
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pwm-led0 = &pwm_led1;
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sw0 = &button0;
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sw1 = &button1;
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sw2 = &button2;
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sw3 = &button3;
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watchdog0 = &wdt31;
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};
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};
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&uart20 {
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current-speed = <115200>;
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pinctrl-0 = <&uart20_default>;
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pinctrl-1 = <&uart20_sleep>;
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pinctrl-names = "default", "sleep";
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};
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&uart30 {
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current-speed = <115200>;
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pinctrl-0 = <&uart30_default>;
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pinctrl-1 = <&uart30_sleep>;
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pinctrl-names = "default", "sleep";
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};
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&pwm20 {
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status = "okay";
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pinctrl-0 = <&pwm20_default>;
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pinctrl-1 = <&pwm20_sleep>;
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pinctrl-names = "default", "sleep";
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};

‎boards/nordic/nrf54lm20pdk/nrf54lm20pdk_nrf54lm20a-pinctrl.dtsi‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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&pinctrl {
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/omit-if-no-ref/ uart20_default: uart20_default {
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group1 {
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psels = <NRF_PSEL(UART_TX, 1, 4)>;
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};
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group2 {
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psels = <NRF_PSEL(UART_RX, 1, 5)>;
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bias-pull-up;
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};
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};
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/omit-if-no-ref/ uart20_sleep: uart20_sleep {
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group1 {
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psels = <NRF_PSEL(UART_TX, 1, 4)>,
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<NRF_PSEL(UART_RX, 1, 5)>;
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low-power-enable;
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};
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};
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/omit-if-no-ref/ pwm20_default: pwm20_default {
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group1 {
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psels = <NRF_PSEL(PWM_OUT0, 1, 7)>;
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};
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};
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/omit-if-no-ref/ pwm20_sleep: pwm20_sleep {
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group1 {
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psels = <NRF_PSEL(PWM_OUT0, 1, 7)>;
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low-power-enable;
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};
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};
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/omit-if-no-ref/ uart30_default: uart30_default {
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group1 {
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psels = <NRF_PSEL(UART_TX, 0, 0)>,
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<NRF_PSEL(UART_RTS, 0, 2)>;
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};
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group2 {
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psels = <NRF_PSEL(UART_RX, 0, 1)>,
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<NRF_PSEL(UART_CTS, 0, 3)>;
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bias-pull-up;
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};
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};
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/omit-if-no-ref/ uart30_sleep: uart30_sleep {
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group1 {
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psels = <NRF_PSEL(UART_TX, 0, 0)>,
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<NRF_PSEL(UART_RX, 0, 1)>,
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<NRF_PSEL(UART_RTS, 0, 2)>,
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<NRF_PSEL(UART_CTS, 0, 3)>;
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low-power-enable;
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};
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};
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/omit-if-no-ref/ spi00_default: spi00_default {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
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<NRF_PSEL(SPIM_MOSI, 2, 2)>,
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<NRF_PSEL(SPIM_MISO, 2, 4)>;
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};
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};
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/omit-if-no-ref/ spi00_sleep: spi00_sleep {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
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<NRF_PSEL(SPIM_MOSI, 2, 2)>,
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<NRF_PSEL(SPIM_MISO, 2, 4)>;
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low-power-enable;
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};
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};
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};

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