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Nov 15, 2024
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samples: benchmarks: coremark: migrate to STM logging on nrf54h20dk #17479

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75889f2
samples: benchmarks: coremark: log end of test in the flash & run mode
kapi-no Nov 5, 2024
12acf9a
samples: benchmarks: coremark: add a new line for visibility
kapi-no Nov 5, 2024
4d3bb9d
samples: benchmarks: coremark: optimize stack for multi thread config
kapi-no Nov 14, 2024
dd330ee
samples: benchmarks: coremark: migrate to STM logging on nrf54h20dk
kapi-no Sep 24, 2024
51c6389
samples: benchmarks: coremark: unify format in different logging modes
kapi-no Nov 5, 2024
8aabb18
samples: benchmarks: coremark: enable logs from the fault handler
kapi-no Nov 15, 2024
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7 changes: 6 additions & 1 deletion doc/nrf/releases_and_maturity/releases/release-notes-changelog.rst
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Expand Up @@ -379,7 +379,12 @@ Wi-Fi samples
Other samples
-------------

|no_changes_yet_note|
* :ref:`coremark_sample` sample:

* Updated:

* Configuration for the :ref:`zephyr:nrf54h20dk_nrf54h20` board to support multi-domain logging using the ARM Coresight STM.
* The logging format in the standard logging mode to align it with the format used in the multi-domain logging mode.

Drivers
=======
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10 changes: 1 addition & 9 deletions samples/benchmarks/coremark/Kconfig.sysbuild
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Expand Up @@ -14,12 +14,4 @@ config APP_CPUNET_RUN
config APP_CPUPPR_RUN
bool "Run the CoreMark benchmark on the PPR core"
depends on SUPPORT_PPRCORE
depends on !BOARD_NRF54H20DK || !APP_CPUNET_RUN
help
Due to the limited number of UART ports on the nRF54H20 DK, you can run the CoreMark
benchmark only on two cores at a time; application core and either radio core or PPR
core.

PPR code is run from RAM. You must use the "nordic-ppr" snippet for the application
core to be able to boot the PPR core. You need to provide the "coremark_SNIPPET=nordic"
build argument.
default y
189 changes: 156 additions & 33 deletions samples/benchmarks/coremark/README.rst
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Expand Up @@ -28,6 +28,44 @@ For the button assignment, see the :ref:`coremark_user_interface` section.
When the benchmark has completed, you can press the same button to restart it.
If you want to run the sample upon startup, enable the :ref:`CONFIG_APP_MODE_FLASH_AND_RUN <CONFIG_APP_MODE_FLASH_AND_RUN>` Kconfig option.

Logging
=======

The logging mode depends on the chosen board target.
The sample supports two distinct modes that are described in the following subsections.

Standard logging
----------------

This logging mode is used by most board targets.
Each core running the CoreMark benchmark has an independent UART instance that is used for logging.

To see all logging information for the multi-core board targets, you must open a terminal for each active core.

The sample configuration sets up the following board targets for standard logging:

* ``nrf52840dk/nrf52840``
* ``nrf52833dk/nrf52833``
* ``nrf52dk/nrf52832``
* ``nrf5340dk/nrf5340/cpuapp``
* ``nrf54l15dk/nrf54l15/cpuapp``

Multi-domain logging
--------------------

This logging mode is used by multi-core board targets that support logging using the ARM Coresight STM.
Each core running the CoreMark benchmark writes its logging information to its own set of STM Extended Stimulus Port (STMESP).
One core in the system is designated to collect all logs and to send them to the chosen UART instance.
The sample supports multi-domain logging in the standalone mode.
See :ref:`zephyr:logging_cs_stm` for more details.

To see all logging information in this logging mode, it is enough to open one terminal.
When the core used for sending the logs to UART is running the CoreMark benchmark, the logging activity is blocked until the benchmark has completed.

The sample configuration sets up the following board targets for multi-domain logging:

* ``nrf54h20dk/nrf54h20/cpuapp``

.. _coremark_user_interface:

User interface
Expand Down Expand Up @@ -146,13 +184,6 @@ SB_CONFIG_APP_CPUPPR_RUN - Enable execution for the PPR core

.. note::
PPR code is run from RAM.
You must use the ``nordic-ppr`` snippet for the application core to be able to boot the PPR core.
Use the build argument ``coremark_SNIPPET=nordic-ppr``.
To build the sample with the execution for the PPR core enabled, run the following command:

.. code-block:: console

west build -b nrf54h20dk/nrf54h20/cpuapp -- -DSB_CONFIG_APP_CPUNET_RUN=n -DSB_CONFIG_APP_CPUPPR_RUN=y -Dcoremark_SNIPPET=nordic-ppr

Building and running
********************
Expand All @@ -176,6 +207,11 @@ Testing
After programming the sample to your development kit, complete the following steps to test it:

1. |connect_terminal|

.. note::
To see all logging information for the multi-core board targets and the standard logging mode, you must open a terminal for each active core.
The ``nrf5340dk/nrf5340/cpuapp`` is an example of such board target.

#. Reset your development kit.
#. To start the test, press the button assigned to the respective core.
For button assignment, refer to the :ref:`coremark_user_interface` section.
Expand All @@ -190,29 +226,116 @@ After programming the sample to your development kit, complete the following ste
#. Wait for the console output for all tested cores.
The results will be similar to the following example:

.. code-block:: console

*** Booting nRF Connect SDK v2.7.0-b6081ebcf502 ***
*** Using Zephyr OS v3.6.99-100befc70c74 ***
I: CoreMark sample for nrf52840dk/nrf52840
I: Press Push button switch 0 to start the test ...
I: Push button switch 0 pressed!
I: CoreMark started! CPU FREQ: 64000000 Hz, threads: 1, data size: 2000; iterations: 2000

2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 400968
Total time (secs): 12.236000
Iterations/Sec : 163.452109
Iterations : 2000
Compiler version : GCC12.2.0
Compiler flags : -O3 + see compiler flags added by Zephyr
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0x4983
Correct operation validated. See README.md for run and reporting rules.
CoreMark 1.0 : 163.452109 / GCC12.2.0 -O3 + see compiler flags added by Zephyr / STACK
I: CoreMark finished! Push Push button switch 0 to restart ...
.. tabs::

.. group-tab:: Standard logging

.. code-block:: console

*** Booting nRF Connect SDK v2.8.99-bd4a30a3a758 ***
*** Using Zephyr OS v3.7.99-02718211f9a9 ***
[00:00:00.261,383] <inf> app: Standard logging mode

[00:00:00.266,967] <inf> app: CoreMark sample for nrf52840dk/nrf52840
[00:00:00.274,139] <inf> app: Press Push button switch 0 to start the test ...

[00:00:01.267,608] <inf> app: Push button switch 0 pressed!
[00:00:01.273,864] <inf> app: CoreMark started! CPU FREQ: 64000000 Hz, threads: 1, data size: 2000; iterations: 2000

2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 401215
Total time (secs): 12.244000
Iterations/Sec : 163.345312
Iterations : 2000
Compiler version : GCC12.2.0
Compiler flags : -O3 + see compiler flags added by Zephyr
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0x4983
Correct operation validated. See README.md for run and reporting rules.
CoreMark 1.0 : 163.345312 / GCC12.2.0 -O3 + see compiler flags added by Zephyr / STACK
[00:00:13.597,778] <inf> app: CoreMark finished! Press Push button switch 0 to restart ...

.. group-tab:: Multi-domain logging

.. code-block:: console

*** Booting nRF Connect SDK v2.8.99-f9add8e14565 ***
*** Using Zephyr OS v3.7.99-02718211f9a9 ***
[00:00:00.208,166] <inf> app/app: Multi-domain logging mode
[00:00:00.208,168] <inf> app/app: This core is used to output logs from all cores to terminal over UART

[00:00:00.208,441] <inf> ppr/app: CoreMark sample for [email protected]/nrf54h20/cpuppr
[00:00:00.208,496] <inf> ppr/app: CoreMark started! CPU FREQ: 16000000 Hz, threads: 1, data size: 2000; iterations: 500

[00:00:01.186,256] <inf> rad/app: CoreMark sample for [email protected]/nrf54h20/cpurad
[00:00:01.186,305] <inf> rad/app: Press Push button 1 to start the test ...

[00:00:01.285,614] <inf> app/app: CoreMark sample for [email protected]/nrf54h20/cpuapp
[00:00:01.285,654] <inf> app/app: Press Push button 0 to start the test ...

[00:00:04.984,744] <inf> app/app: Push button 0 pressed!
[00:00:04.984,753] <inf> app/app: CoreMark started! CPU FREQ: 320000000 Hz, threads: 1, data size: 2000; iterations: 10000

[00:00:04.984,755] <inf> app/app: Logging is blocked for all cores until this core finishes the CoreMark benchmark

[00:00:05.714,470] <inf> rad/app: Push button 1 pressed!
[00:00:05.714,486] <inf> rad/app: CoreMark started! CPU FREQ: 256000000 Hz, threads: 1, data size: 2000; iterations: 10000

2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 13471150
Total time (secs): 13.471000
Iterations/Sec : 37.116769
Iterations : 500
Compiler version : GCC12.2.0
Compiler flags : -O3 + see compiler flags added by Zephyr
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0xa14c
Correct operation validated. See README.md for run and reporting rules.
CoreMark 1.0 : 37.116769 / GCC12.2.0 -O3 + see compiler flags added by Zephyr / STACK
[00:00:13.595,072] <inf> ppr/app: CoreMark finished! Press the reset button to restart...

2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 11436744
Total time (secs): 11.436000
Iterations/Sec : 874.431619
Iterations : 10000
Compiler version : GCC12.2.0
Compiler flags : -O3 + see compiler flags added by Zephyr
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0x988c
Correct operation validated. See README.md for run and reporting rules.
CoreMark 1.0 : 874.431619 / GCC12.2.0 -O3 + see compiler flags added by Zephyr / STACK
[00:00:16.446,916] <inf> app/app: CoreMark finished! Press Push button 0 to restart ...

2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 14290211
Total time (secs): 14.290000
Iterations/Sec : 699.790063
Iterations : 10000
Compiler version : GCC12.2.0
Compiler flags : -O3 + see compiler flags added by Zephyr
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0x988c
Correct operation validated. See README.md for run and reporting rules.
CoreMark 1.0 : 699.790063 / GCC12.2.0 -O3 + see compiler flags added by Zephyr / STACK
[00:00:19.911,390] <inf> rad/app: CoreMark finished! Press Push button 1 to restart ...
6 changes: 6 additions & 0 deletions samples/benchmarks/coremark/boards/nrf52833dk_nrf52833.conf
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@@ -0,0 +1,6 @@
#
# Copyright (c) 2024 Nordic Semiconductor ASA
#
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause

CONFIG_LOG_MODE_IMMEDIATE=y
6 changes: 6 additions & 0 deletions samples/benchmarks/coremark/boards/nrf52840dk_nrf52840.conf
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#
# Copyright (c) 2024 Nordic Semiconductor ASA
#
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause

CONFIG_LOG_MODE_IMMEDIATE=y
6 changes: 6 additions & 0 deletions samples/benchmarks/coremark/boards/nrf52dk_nrf52832.conf
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#
# Copyright (c) 2024 Nordic Semiconductor ASA
#
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause

CONFIG_LOG_MODE_IMMEDIATE=y
2 changes: 2 additions & 0 deletions samples/benchmarks/coremark/boards/nrf5340dk_nrf5340_cpuapp.conf
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Expand Up @@ -4,3 +4,5 @@
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause

CONFIG_SOC_NRF53_CPUNET_ENABLE=y

CONFIG_LOG_MODE_IMMEDIATE=y
6 changes: 6 additions & 0 deletions samples/benchmarks/coremark/boards/nrf5340dk_nrf5340_cpunet.conf
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#
# Copyright (c) 2024 Nordic Semiconductor ASA
#
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause

CONFIG_LOG_MODE_IMMEDIATE=y
9 changes: 9 additions & 0 deletions samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.conf
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Expand Up @@ -4,3 +4,12 @@
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause

CONFIG_COREMARK_ITERATIONS=10000

# Kconfigs required for the STM standalone logging, imported from the nordic-log-stm snippet.
CONFIG_TEST_LOGGING_DEFAULTS=n
CONFIG_LOG_FRONTEND=y
CONFIG_LOG_FRONTEND_ONLY=y
CONFIG_LOG_FRONTEND_STMESP=y
CONFIG_LOG_FRONTEND_STMESP_FSC=y

CONFIG_UART_ASYNC_API=y
20 changes: 20 additions & 0 deletions samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
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Expand Up @@ -29,3 +29,23 @@
owned-channels = <7>;
status = "okay";
};

/* DTS nodes required to run the cpuppr target. */
&cpuppr_vpr {
status = "okay";
};

&cpuppr_ram3x_region {
status = "okay";
};

/* DTS nodes required for the STM standalone logging, imported from the nordic-log-stm snippet. */
&tbm {
status = "okay";
};

&tddconf {
status = "okay";
etrsources = <(NRF_TDDCONF_SOURCE_STMMAINCORE | NRF_TDDCONF_SOURCE_STMPPR)>;
portconfig = <0>;
};
14 changes: 14 additions & 0 deletions samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuppr.conf
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Expand Up @@ -4,3 +4,17 @@
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause

CONFIG_COREMARK_ITERATIONS=500

# Disable the UART console Kconfig to make Kconfig configuration with the DTS configuration.
CONFIG_UART_CONSOLE=n

# Kconfigs required for the STM standalone logging, imported from the nordic-log-stm snippet.
CONFIG_TEST_LOGGING_DEFAULTS=n
CONFIG_LOG_FRONTEND=y
CONFIG_LOG_FRONTEND_ONLY=y
CONFIG_LOG_FRONTEND_STMESP=y
CONFIG_LOG_FRONTEND_STMESP_FSC=y

# Disable the NCS boot banner - the application core is responsible for printing the boot banner.
CONFIG_NCS_BOOT_BANNER=n
CONFIG_BOOT_BANNER=n
8 changes: 7 additions & 1 deletion samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuppr.overlay
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Expand Up @@ -4,4 +4,10 @@
* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
*/

/* Intentionally left empty to overwrite default app.overlay. */
/* Disable the default UART node for the pepper core, as logs are forwarded
* with STM and the application core UART. This setting also prevents access
* issues to the same UART instance from two or more different cores.
*/
&uart135 {
status = "disabled";
};
14 changes: 14 additions & 0 deletions samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpurad.conf
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Expand Up @@ -4,3 +4,17 @@
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause

CONFIG_COREMARK_ITERATIONS=10000

# Disable the UART console Kconfig to make Kconfig configuration with the DTS configuration.
CONFIG_UART_CONSOLE=n

# Kconfigs required for the STM standalone logging, imported from the nordic-log-stm snippet.
CONFIG_TEST_LOGGING_DEFAULTS=n
CONFIG_LOG_FRONTEND=y
CONFIG_LOG_FRONTEND_ONLY=y
CONFIG_LOG_FRONTEND_STMESP=y
CONFIG_LOG_FRONTEND_STMESP_FSC=y

# Disable the NCS boot banner - the application core is responsible for printing the boot banner.
CONFIG_NCS_BOOT_BANNER=n
CONFIG_BOOT_BANNER=n
15 changes: 15 additions & 0 deletions samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpurad.overlay
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Expand Up @@ -40,3 +40,18 @@
owned-channels = <6>;
status = "okay";
};

/* Disable the default UART node for the radio core, as logs are forwarded
* with STM and the application core UART. This setting also prevents access
* issues to the same UART instance from two or more different cores.
*/
&uart135 {
status = "disabled";
};

/* DTS nodes required for the STM standalone logging, imported from the nordic-log-stm snippet. */
&tddconf {
status = "okay";
etrsources = <(NRF_TDDCONF_SOURCE_STMMAINCORE)>;
portconfig = <0>;
};
2 changes: 2 additions & 0 deletions samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuapp.conf
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Expand Up @@ -4,3 +4,5 @@
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause

CONFIG_COREMARK_ITERATIONS=4000

CONFIG_LOG_MODE_IMMEDIATE=y
4 changes: 3 additions & 1 deletion samples/benchmarks/coremark/prj.conf
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Expand Up @@ -13,9 +13,11 @@ CONFIG_MAIN_STACK_SIZE=4096
CONFIG_COMPILER_OPT="-O3"

# Config results output
# The default logging level is set to the OFF level.
# Kernel error logging is enabled to notify the developer about system faults.
CONFIG_LOG=y
CONFIG_LOG_MODE_MINIMAL=y
CONFIG_LOG_DEFAULT_LEVEL=0
CONFIG_KERNEL_LOG_LEVEL_ERR=y
CONFIG_CBPRINTF_FP_SUPPORT=y

CONFIG_GPIO=y
Expand Down
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