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Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,14 @@
};
};

&cpuflpr_rram {
reg = <0x179800 DT_SIZE_K(14)>;
};

&cpuflpr_code_partition {
reg = <0x0 DT_SIZE_K(14)>;
};

&cpuflpr_sram {
reg = <0x2003c800 DT_SIZE_K(14)>;
ranges = <0x0 0x2003c800 0x3800>;
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Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,14 @@
};
};

&cpuflpr_rram {
reg = <0x17a000 DT_SIZE_K(12)>;
};

&cpuflpr_code_partition {
reg = <0x0 DT_SIZE_K(12)>;
};

&cpuflpr_sram {
reg = <0x2003d000 DT_SIZE_K(12)>;
ranges = <0x0 0x2003d000 0x3000>;
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Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,14 @@
};
};

&cpuflpr_rram {
reg = <0x17a000 DT_SIZE_K(12)>;
};

&cpuflpr_code_partition {
reg = <0x0 DT_SIZE_K(12)>;
};

&cpuflpr_sram {
reg = <0x2003d000 DT_SIZE_K(12)>;
ranges = <0x0 0x2003d000 0x3000>;
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Original file line number Diff line number Diff line change
Expand Up @@ -10,9 +10,8 @@
#address-cells = <1>;
#size-cells = <1>;

cpuflpr_code_partition: image@165000 {
/* FLPR core code partition */
reg = <0x165000 DT_SIZE_K(96)>;
cpuflpr_code_partition: image@179800 {
reg = <0x179800 DT_SIZE_K(14)>;
};

sram_rx: memory@2003b800 {
Expand Down Expand Up @@ -48,6 +47,10 @@
};
};

&cpuapp_rram {
reg = <0x0 DT_SIZE_K(1510)>;
};

&cpuapp_sram {
reg = <0x20000000 DT_SIZE_K(242)>;
ranges = <0x0 0x20000000 0x3d000>;
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Original file line number Diff line number Diff line change
Expand Up @@ -10,9 +10,8 @@
#address-cells = <1>;
#size-cells = <1>;

cpuflpr_code_partition: image@165000 {
/* FLPR core code partition */
reg = <0x165000 DT_SIZE_K(96)>;
cpuflpr_code_partition: image@17a000 {
reg = <0x17a000 DT_SIZE_K(12)>;
};

sram_rx: memory@2003c000 {
Expand Down Expand Up @@ -46,6 +45,10 @@
};
};

&cpuapp_rram {
reg = <0x0 DT_SIZE_K(1512)>;
};

&cpuapp_sram {
reg = <0x20000000 DT_SIZE_K(244)>;
ranges = <0x0 0x20000000 0x3d000>;
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -10,9 +10,8 @@
#address-cells = <1>;
#size-cells = <1>;

cpuflpr_code_partition: image@165000 {
/* FLPR core code partition */
reg = <0x165000 DT_SIZE_K(96)>;
cpuflpr_code_partition: image@17a000 {
reg = <0x17a000 DT_SIZE_K(12)>;
};

sram_rx: memory@2003c000 {
Expand Down Expand Up @@ -41,6 +40,10 @@
};
};

&cpuapp_rram {
reg = <0x0 DT_SIZE_K(1512)>;
};

&cpuapp_sram {
reg = <0x20000000 DT_SIZE_K(244)>;
ranges = <0x0 0x20000000 0x3d000>;
Expand Down
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