Replace SDFW with IronSide SE

CMakeLists.txt

@@ -35,3 +35,9 @@ add_subdirectory(subsys)
 add_subdirectory(modules)
 add_subdirectory(drivers)
 add_subdirectory(tests)
+
+# TEMPHACK: Add a source file generated by cmake/sysbuild/periphconf_migrate.cmake
+if(CONFIG_NRF_HALTIUM_GENERATE_UICR)
+  file(TOUCH ${PROJECT_BINARY_DIR}/periphconf_migrated.c)
+  zephyr_sources(${PROJECT_BINARY_DIR}/periphconf_migrated.c)
+endif()

CODEOWNERS

@@ -537,6 +537,7 @@
 /samples/sensor/bme68x_iaq/               @nrfconnect/ncs-cia
 /samples/nrf5340/empty_app_core/          @nrfconnect/ncs-si-muffin
 /samples/nrf5340/extxip_smp_svr/          @nrfconnect/ncs-pluto
+/samples/nrf54h20/empty_app_core/         @nrfconnect/ncs-aurora
 /samples/nrf_compress/                    @nordicjm
 /samples/nrf_profiler/                    @nrfconnect/ncs-si-bluebagel
 /samples/nrf_rpc/protocols_serialization/ @nrfconnect/ncs-protocols-serialization

applications/machine_learning/configuration/nrf54h20dk_nrf54h20_cpuapp/app.overlay

@@ -40,6 +40,16 @@
 			label = "Green LED 3";
 		};
 	};
+
+	reserved-memory {
+		cpuppr_code_data: memory@2fc00000 {
+			reg = <0x2fc00000 0xf200>;
+		};
+
+		ram3x_agg_area0: memory@2fc0f200 {
+			reg = <0x2fc0f200 0x600>;
+		};
+	};
 };
 
 &cpuppr_vevif {
@@ -50,49 +60,21 @@ ipc1: &cpuapp_cpuppr_ipc {
 	status = "okay";
 };
 
-/* Expand APP slot partition and remove DFU partition. */
-/delete-node/ &cpuapp_rx_partitions;
-/delete-node/ &cpuapp_rw_partitions;
+/delete-node/ &cpuapp_slot0_partition;
+/delete-node/ &cpurad_slot0_partition;
 
-&cpuppr_ram3x_region {
-	cpuppr_code_data: memory@0 {
-		reg = <0x0 0xf200>;
-	};
+&mram1x {
+	partitions {
+		slot0_partition: cpuapp_slot0_partition: partition@30000 {
+			reg = <0x30000 0x82000>;
+		};
 
-	ram3x_agg_area0: memory@f200{
-		reg = <0xf200 0x600>;
+		cpurad_slot0_partition: partition@b2000 {
+			reg = <0xb2000 0x32000>;
+		};
 	};
 };
 
-&mram1x {
-       cpuapp_rx_partitions: cpuapp-rx-partitions {
-	       compatible = "nordic,owned-partitions", "fixed-partitions";
-	       status = "okay";
-	       nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RXS>;
-	       #address-cells = <1>;
-	       #size-cells = <1>;
-
-	       cpuapp_slot0_partition: partition@a6000 {
-		       reg = <0xa6000 DT_SIZE_K(512)>;
-	       };
-
-	       cpuppr_code_partition: partition@126000 {
-		       reg = <0x126000 DT_SIZE_K(64)>;
-	       };
-       };
-
-       cpuapp_rw_partitions: cpuapp-rw-partitions {
-	       compatible = "nordic,owned-partitions", "fixed-partitions";
-	       status = "okay";
-	       nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RW>;
-	       #address-cells = < 0x1 >;
-	       #size-cells = < 0x1 >;
-
-	       storage_partition: partition@136000 {
-		       reg = < 0x136000 DT_SIZE_K(24) >;
-	       };
-       };
-};
 
 /* Remove DTS nodes associated with the cpuflpr target as they refer to the
  * cpuflpr_code_partition label from the cpuapp_rx_partitions node. The label has

applications/machine_learning/remote/boards/nrf54h20dk_nrf54h20_cpuppr.overlay

@@ -14,54 +14,33 @@
 		memory-region = <&ram3x_agg_area0>;
 		status = "okay";
 	};
-};
 
-/* Expand APP slot partition and remove DFU partition. */
-/delete-node/ &cpuapp_rx_partitions;
-/delete-node/ &cpuapp_rw_partitions;
 
-/*
- * Place aggregator buffers in PPR memory region.
- */
-&cpuppr_ram3x_region {
-	cpuppr_code_data: memory@0 {
-		reg = <0x0 0xf200>;
-	};
+	reserved-memory {
+		cpuppr_code_data: memory@2fc00000 {
+			reg = <0x2fc00000 0xf200>;
+		};
 
-	ram3x_agg_area0: memory@f200{
-		reg = <0xf200 0x600>;
+		ram3x_agg_area0: memory@2fc0f200 {
+			reg = <0x2fc0f200 0x600>;
+		};
 	};
 };
 
+/delete-node/ &cpuapp_slot0_partition;
+/delete-node/ &cpurad_slot0_partition;
+
 /* This duplicates the Application core configuration to build PPR image under valid address. */
 &mram1x {
-       cpuapp_rx_partitions: cpuapp-rx-partitions {
-	       compatible = "nordic,owned-partitions", "fixed-partitions";
-	       status = "okay";
-	       nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RXS>;
-	       #address-cells = <1>;
-	       #size-cells = <1>;
-
-	       cpuapp_slot0_partition: partition@a6000 {
-		       reg = <0xa6000 DT_SIZE_K(512)>;
-	       };
-
-	       cpuppr_code_partition: partition@126000 {
-		       reg = <0x126000 DT_SIZE_K(64)>;
-	       };
-       };
-
-       cpuapp_rw_partitions: cpuapp-rw-partitions {
-	       compatible = "nordic,owned-partitions", "fixed-partitions";
-	       status = "okay";
-	       nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RW>;
-	       #address-cells = < 0x1 >;
-	       #size-cells = < 0x1 >;
-
-	       storage_partition: partition@136000 {
-		       reg = < 0x136000 DT_SIZE_K(24) >;
-	       };
-       };
+	partitions {
+		cpuapp_slot0_partition: slot0_partition: partition@30000 {
+			reg = <0x30000 0x82000>;
+		};
+
+		cpurad_slot0_partition: partition@b2000 {
+			reg = <0xb2000 0x32000>;
+		};
+	};
 };
 
 ipc1: &cpuapp_cpuppr_ipc {

applications/machine_learning/sysbuild/ipc_radio/boards/nrf54h20dk_nrf54h20_cpurad.overlay

@@ -18,37 +18,3 @@
 &cpurad_dma_region {
 	status = "disabled";
 };
-
-/* Expand APP slot partition and remove DFU partition. */
-/delete-node/ &cpuapp_rx_partitions;
-/delete-node/ &cpuapp_rw_partitions;
-
-&mram1x {
-	cpuapp_rx_partitions: cpuapp-rx-partitions {
-		compatible = "nordic,owned-partitions", "fixed-partitions";
-		status = "disabled";
-		nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RXS>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		cpuapp_slot0_partition: partition@a6000 {
-			reg = <0xa6000 DT_SIZE_K(512)>;
-		};
-
-		cpuppr_code_partition: partition@126000 {
-			reg = <0x126000 DT_SIZE_K(64)>;
-		};
-	};
-
-	cpuapp_rw_partitions: cpuapp-rw-partitions {
-		compatible = "nordic,owned-partitions", "fixed-partitions";
-		status = "disabled";
-		nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RW>;
-		#address-cells = < 0x1 >;
-		#size-cells = < 0x1 >;
-
-		storage_partition: partition@136000 {
-			reg = < 0x136000 DT_SIZE_K(24) >;
-		};
-	};
-};

boards/shields/coverage_support/boards/nrf54h20dk_nrf54h20_cpuapp.overlay

@@ -4,26 +4,6 @@
  * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
  */
 
-/* Delete current app definition to redefine belowe */
-/delete-node/ &cpuapp_slot0_partition;
-
-/* Extend by 160 KB, taken from rad */
-&cpuapp_rx_partitions {
-	cpuapp_slot0_partition: partition@6C000 {
-		reg = <0x6C000 DT_SIZE_K(480)>;
-	};
-};
-
-/* Shrink by 160 KB */
-&cpurad_slot0_partition {
-	reg = <0x54000 DT_SIZE_K(96)>;
-};
-
 &uart136 {
 	hw-flow-control;
 };
-
-/* To disable SDFW_SERVICES to save RAM */
-&cpusec_cpuapp_ipc {
-	status = "disabled";
-};

cmake/sysbuild/periphconf_migrate.cmake

@@ -0,0 +1,66 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+# This file includes extra sysbuild POST_CMAKE logic to assist with
+# autogenerating an IronSide SE compatible UICR.
+#
+# It is enabled when SB_CONFIG_NRF_PERIPHCONF_MIGRATE=y is set and
+# one of the sysbuild images has CONFIG_NRF_HALTIUM_GENERATE_UICR=y.
+# It uses nrf-regtool to produce an extra source file for that image
+# (periphconf_migrated.c) based on multiple image devicetrees.
+#
+# NOTE: This is a temporary solution for NCS. The planned solution
+# for upstream Zephyr will not require nrf-regtool.
+
+set(ironside_uicr_images "")
+set(ironside_uicr_main_image)
+foreach(image ${POST_CMAKE_IMAGES})
+  sysbuild_get(${image}_54h20_app IMAGE ${image} VAR CONFIG_SOC_NRF54H20_CPUAPP KCONFIG)
+  sysbuild_get(${image}_54h20_rad IMAGE ${image} VAR CONFIG_SOC_NRF54H20_CPURAD KCONFIG)
+  if(${image}_54h20_app OR ${image}_54h20_rad)
+    list(APPEND ironside_uicr_images ${image})
+    if(NOT DEFINED ironside_uicr_main_image)
+      sysbuild_get(image_generates_uicr IMAGE ${image} VAR CONFIG_NRF_HALTIUM_GENERATE_UICR KCONFIG)
+      if(image_generates_uicr)
+        set(ironside_uicr_main_image ${image})
+      endif()
+    endif()
+  endif()
+endforeach()
+if(DEFINED ironside_uicr_main_image)
+  find_program(NRF_REGTOOL nrf-regtool REQUIRED)
+  set(nrf_regtool_cmd
+    COMMAND
+    ${CMAKE_COMMAND} -E env PYTHONPATH=${ZEPHYR_BASE}/scripts/dts/python-devicetree/src
+    ${NRF_REGTOOL}
+  )
+  ExternalProject_Get_Property(${ironside_uicr_main_image} BINARY_DIR)
+  set(nrf_regtool_migrate_cmd
+    ${nrf_regtool_cmd}
+    uicr-migrate
+    --edt-pickle-file ${BINARY_DIR}/zephyr/edt.pickle
+    --output-periphconf-file ${BINARY_DIR}/zephyr/periphconf_migrated.c
+  )
+  foreach(image ${ironside_uicr_images})
+    ExternalProject_Get_Property(${image} BINARY_DIR)
+    sysbuild_get(image_soc IMAGE ${image} VAR CONFIG_SOC KCONFIG)
+    set(image_uicr_hex ${PROJECT_BINARY_DIR}/uicr_${image}.hex)
+    message(STATUS "Running nrf-regtool uicr-compile for ${image}")
+    execute_process(
+      ${nrf_regtool_cmd}
+      uicr-compile
+      --edt-pickle-file ${BINARY_DIR}/zephyr/edt.pickle
+      --product-name ${image_soc}
+      --output-file ${image_uicr_hex}
+      WORKING_DIRECTORY ${APPLICATION_SOURCE_DIR}
+      COMMAND_ERROR_IS_FATAL ANY
+    )
+    list(APPEND nrf_regtool_migrate_cmd --uicr-hex-file ${image_uicr_hex})
+  endforeach()
+  message(STATUS "Running nrf-regtool uicr-migrate for ${ironside_uicr_main_image}")
+  execute_process(
+    ${nrf_regtool_migrate_cmd}
+    WORKING_DIRECTORY ${APPLICATION_SOURCE_DIR}
+    COMMAND_ERROR_IS_FATAL ANY
+  )
+endif()

cmake/sysbuild/suit_provisioning.cmake

@@ -227,10 +227,9 @@ function (generate_mpi_area area)
   message(INFO " Generate merged MPI for ${area} (${output})")
 endfunction()
 
-if((DEFINED SB_CONFIG_SOC_SERIES_NRF54HX) OR
-    (DEFINED SB_CONFIG_SOC_SERIES_NRF92X))
+if(DEFINED SB_CONFIG_SOC_SERIES_NRF92X)
   configure_storage_address_cache()
-endif() # SB_CONFIG_SOC_SERIES_NRF54HX OR SB_CONFIG_SOC_SERIES_NRF92X
+endif() # SB_CONFIG_SOC_SERIES_NRF92X
 
 if(DEFINED SB_CONFIG_SUIT_MPI_GENERATE)
   include(${CMAKE_CURRENT_LIST_DIR}/suit_provisioning_${SB_CONFIG_SOC}.cmake)

doc/nrf/drivers/mspi_sqspi.rst

@@ -69,10 +69,6 @@ See the following configuration example for the nRF54L15 SoC:
 
 	/ {
 		reserved-memory {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
 			softperiph_ram: memory@2003c000 {
 				reg = <0x2003c000 0x4000>;
 				ranges = <0 0x2003c000 0x4000>;
@@ -145,31 +141,35 @@ The following example configuration for the nRF54H20 SoC sets up the necessary p
 	/delete-node/ &cpuflpr_cpuapp_ipc_shm;
 	/delete-node/ &cpuapp_cpuflpr_ipc;
 
-	&ram21_region {
-		status = "okay";
-
-		softperiph_ram: memory@0 {
-			reg = <0 0x4000>;
-			ranges;
+	/ {
+		reserved-memory {
 			#address-cells = <1>;
 			#size-cells = <1>;
+			ranges;
 
-			sqspi: sqspi@3e00 {
-				compatible = "nordic,nrf-sqspi";
+			softperiph_ram: memory@2f890000 {
+				reg = <0x2f890000 0x4000>;
+				ranges;
 				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <0x3e00 0x200>;
-				zephyr,pm-device-runtime-auto;
-				memory-regions = <&sqspi_buffers>;
+				#size-cells = <1>;
+
+				dut: sqspi: sqspi@3e00 {
+					compatible = "nordic,nrf-sqspi";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x3e00 0x200>;
+					zephyr,pm-device-runtime-auto;
+					memory-regions = <&sqspi_buffers>;
+				};
 			};
-		};
 
-		sqspi_buffers: memory@4000 {
-			compatible = "zephyr,memory-region";
-			reg = <0x4000 0x4000>;
-			#memory-region-cells = <0>;
-			zephyr,memory-region = "SQSPI_BUFFERS";
-			zephyr,memory-attr = <DT_MEM_CACHEABLE>;
+			sqspi_buffers: memory@2f894000 {
+				compatible = "zephyr,memory-region";
+				reg = <0x2f894000 0x4000>;
+				#memory-region-cells = <0>;
+				zephyr,memory-region = "SQSPI_BUFFERS";
+				zephyr,memory-attr = <DT_MEM_CACHEABLE>;
+			};
 		};
 	};
 

lib/fprotect/Kconfig

@@ -50,6 +50,7 @@ menuconfig FPROTECT
 	bool "Enable FPROTECT"
 	depends on SOC_FAMILY_NORDIC_NRF
 	depends on !(SOC_SERIES_NRF54LX && IS_SECURE_BOOTLOADER)
+	depends on !SOC_SERIES_NRF54HX
 	default y if MCUBOOT && (!SOC_SERIES_NRF54LX || (SOC_SERIES_NRF54LX && MCUBOOT_MCUBOOT_IMAGE_NUMBER = -1))
 	#enabled for nRF54L SoC's when MCUboot is the only one bootloader
 	select NRFX_RRAMC if SOC_SERIES_NRF54LX

samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.overlay

@@ -40,10 +40,6 @@
 	status = "okay";
 };
 
-&cpuppr_ram3x_region {
-	status = "okay";
-};
-
 /* DTS nodes required for the STM standalone logging, imported from the nordic-log-stm snippet. */
 &tbm {
 	status = "okay";